메뉴 건너뛰기




Volumn 12, Issue , 2004, Pages 155-161

Flexibility measurement of domain-specific reconfigurable hardware

Author keywords

Flexibility; Programmable Hardware; Reconfigurable Hardware

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MICROPROCESSOR CHIPS; PROGRAMMABLE LOGIC CONTROLLERS;

EID: 2442526615     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/968280.968303     Document Type: Conference Paper
Times cited : (11)

References (9)
  • 6
    • 0032182384 scopus 로고    scopus 로고
    • Characterization and parameterized generation of synthetic combinational benchmark circuits
    • October
    • M. Hutton, J. Rose, J. Grossman, and D. Corneil, "Characterization and Parameterized Generation of Synthetic Combinational Benchmark Circuits", IEEE Transactions on CAD, Vol. 17, No. 10, pp. 985-996, October 1998.
    • (1998) IEEE Transactions on CAD , vol.17 , Issue.10 , pp. 985-996
    • Hutton, M.1    Rose, J.2    Grossman, J.3    Corneil, D.4
  • 7
    • 0035242894 scopus 로고    scopus 로고
    • Structural analysis and generation of synthetic digital circuits with memory
    • February
    • S. Wilton, J. Rose, Z. Vranesic, "Structural Analysis and Generation of Synthetic Digital Circuits with Memory", IEEE Transactions on VLSI, Vol. 9, No. 1, pp. 223-226, February 2001.
    • (2001) IEEE Transactions on VLSI , vol.9 , Issue.1 , pp. 223-226
    • Wilton, S.1    Rose, J.2    Vranesic, Z.3
  • 8
    • 0036683878 scopus 로고    scopus 로고
    • Automatic generation of synthetic sequential benchmark circuits
    • August
    • M. Hutton, J. Rose and D. Corneil, "Automatic Generation of Synthetic Sequential Benchmark Circuits", IEEE Transactions on CAD, Vol. 21, No. 8, pp. 928-940, August 2002.
    • (2002) IEEE Transactions on CAD , vol.21 , Issue.8 , pp. 928-940
    • Hutton, M.1    Rose, J.2    Corneil, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.