Morphable multipliers

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2438 LNCS, Issue , 2002, Pages 647-656

  Chiricescu, Silviu ^a   Schuette, Michael ^a   Glinton, Robin ^b   Schmit, Herman ^b  

^a MOTOROLA INC   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATION THEORY; RECONFIGURABLE ARCHITECTURES;

ADDER CELLS; EMBEDDED PROCESSORS; MAXIMUM COVERS; MAXIMUM SPEED; MULTIPLIER DESIGN; PERFORMANCE IMPACT; TIMING SLACK; TREE MULTIPLIER;

ADDERS;

EID: 79955129768     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46117-5_67     Document Type: Conference Paper

References (9)

1. R. Razdan and M. D. Smith, "A high-performance microarchitecture with hardware-programmable functional units," in Proceedings of the 27th Annual International Symposium on Microarchitecture, pp. 172-80, IEEE/ACM, Nov. 1994.
2. S. Hauck, T. Fry, M. Hosler, and J. P. Kao, "The Chimaera reconfigurable functional unit," in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 87-96, April 1997.
3. J. Hauser and J. Wawrzynek, "Garp: A MIPS processor with a reconfigurable coprocessor," in IEEE Symposium on FPGAs for Custom Computing Machines, pp. 24-33, April 1997.
4. A. Peleg, S. Wilkie, and U. Weiser, "Intel mmx for multimedia pcs," Communications of the ACM, vol. 40, no. 1, pp. 24-38, 1997.
5. S. D. Haynes and P. Y. K. Cheung, "Configurable multiplier blocks for embedding in FPGAs," IEE Electronic Letters, vol. 34, pp. 638-639, Apr. 1998. (Pubitemid 128558418)
6. S. D. Haynes, A. B. Ferrari, and P. Y. K. Cheung, "Flexible Reconfigurable Multiplier Blocks Suitable for Enhancing the Architecture of FPGAs," in IEEE 1999 Custom Integrated Circuits Conference, pp. 191-194, Apr. 1999.
7. G. Even, S. M. Mueller, and P.-M. Seidel, "A Dual Mode IEEE Multiplier," in Proceedings IEEE International Conference on Innovative Systems in Silicon, pp. 282-289, 1997.
8. P. Stelling, C. Martel, V. G. Oklobdzija, and P. Ravi, "Optimal Circuits for Parallel Multipliers," IEEE Transactions on Computers, vol. 47, pp. 273-285, Mar. 1998. (Pubitemid 128737461)
9. Z. Galil, S. Micali, and H. Gabow, "Maximal Weighted Matching on General Graphs," in Proceedings of 23rd Annual IEEE Symposium on Foundations of Computer Science, pp. 255-261, 1982.