Analysis and comparison of low-voltage CML D-Latch

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 2, Issue , 2002, Pages 737-740

  Alioto, M ^a   Mita, R ^a   Palumbo, G ^a  

^a UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

D-LATCH; DELAY MODELS; DESIGN STRATEGIES; HIGH SPEED; LOW POWER; LOW-POWER DESIGN; LOW-VOLTAGE; POWER DISSIPATION; POWER-DELAY PRODUCTS; SPICE SIMULATIONS;

COMPUTER SIMULATION;

SPEED;

EID: 27644459320     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2002.1046274     Document Type: Conference Paper

References (8)

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7. M. Alioto - G. Palumbo, "Modeling and optimized design of current mode MUX/XOR and D Flip-Flop," IEEE Trans. on CAS part II, V. 47, No.5, pp.452-461, May, '00.
8. M. Alioto - G. Palumbo, "CML and ECL: optimized design and comparison," IEEE Trans. on CAS part I, Vol.46, No.11, pp. 1330-1341, November 1999.