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Volumn 33, Issue 10, 1998, Pages 1568-1571

New dynamic flip-flops for high-speed dual-modulus prescaler

Author keywords

CMOS integrated circuits; Flip flops; High speed circuits; Prescaler

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COUNTING CIRCUITS; PIPELINE PROCESSING SYSTEMS;

EID: 0032186543     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.720406     Document Type: Article
Times cited : (103)

References (9)
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    • Yuan, J.1    Svensson, C.2
  • 5
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    • Q. Huang and R. Rogenmoser. "Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks," IEEE J. Solid-State Circuits, vol. 31. pp. 456-465. Mar. 1996.
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    • Huang, Q.1    Rogenmoser, R.2
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    • A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop
    • May
    • B. Chang, J. Park, and W. Kim. "A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flop." IEEE J. Solid-State Circuits, vol. 31, pp. 749-752, May 1996.
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    • Chang, B.1    Park, J.2    Kim, W.3
  • 7
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    • High-speed architecture for a programmable frequency divider and a dual-modulus prescaler
    • May
    • P. Larsson, "High-speed architecture for a programmable frequency divider and a dual-modulus prescaler." IEEE J. Solid-State Circuits. vol. 31, pp. 744-748, May 1996.
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    • Larsson, P.1
  • 8
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    • Skew safety and logic flexibility in a true single phase clocked system
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  • 9
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    • R. Rogenmoser and Q. Huang. "An 80OMHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops." IEEE J. Solid-State Circuits. vol. 31. pp. 401-409, Mar. 1996.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.