Some optimizations of hardware multiplication by constant matrices

IEEE Transactions on Computers

Volumn 54, Issue 10, 2005, Pages 1271-1282

  Boullis, Nicolas ^a   Tisserand, Arnaud ^a  

^a UNIVERSITÉ DE LYON   (France)

Author keywords

Common subexpressions sharing; Computer arithmetic; FIR filter; Multiplication by constants

Indexed keywords

COMPUTER HARDWARE; DIGITAL FILTERS; EVOLUTIONARY ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; OPTIMIZATION; PATTERN MATCHING;

COMMON SUBEXPRESSIONS SHARING; COMPUTER ARITHMETIC; HARDWARE MULTIPLICATION;

DIGITAL ARITHMETIC;

EID: 27444433439     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2005.168     Document Type: Article

References (28)

1. D.J. Magenheimer, L. Peters, K.W. Pettis, and D. Zuras, "Integer Multiplication and Division on the HP Precision Architecture," IEEE Trans. Computers, vol. 37, no. 8, pp. 980-990, Aug. 1988.
2. A.D. Booth, "A Signed Binary Multiplication Technique," Quarterly J. Mechanical Applications of Math., vol. IV, no. 2, pp. 236-240, 1951.
3. R. Bernstein, "Multiplication by Integer Constants," Software - Practice and Experience, vol. 16, no. 7, pp. 641-652, July 1986.
4. N. Boullis and A. Tisserand, "Some Optimizations of Hardware Multiplication by Constant Matrices," Proc. 16th IEEE Symp. Computer Arithmetic (ARITH 16), J.-C. Bajard and M. Schulte, eds., pp. 20-27, June 2003.
5. M. Potkonjak, M.B. Srivastava, and A.P. Chandrakasan, "Multiple Constant Multiplications: Efficient and Versatile Framework and Algorithms for Exploring Common Subexpression Elimination," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 2, pp. 151-165, Feb. 1996.
6. M.D. Ercegovac and T. Lang, Digital Arithmetic. Morgan Kaufmann, 2003.
7. M.J. Flynn and S.F. Oberman, Advanced Computer Arithmetic Design. Wiley-Interscience, 2001.
8. R.I. Hartley, "Subexpression Sharing in Filters Using Canonic Signed Digit Multipliers," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 43, no. 10, pp. 677-688, Oct. 1996.
9. K.D. Chapman, "Fast Integer Multipliers Fit in FPGAs," EDN Magazine, May 1994.
10. S. Yu and E.E. Swartzlander, "DCT Implementation with Distributed Arithmetic," IEEE Trans. Computers, vol. 50, no. 9, pp. 985-991, Sept. 2001.
11. P. Boonyanant and S. Tantaratana, "FIR Filters with Punctured Radix-8 Symmetric Coefficients: Design and Multiplier-Free Realizations," Circuits Systems Signal Processing, vol. 21, no. 4, pp 345-367, 2002.
12. C.K.S. Pun, S.C. Chan, K.S. Yeung, and K.L. Ho, "On the Design and Implementation of FIR and IIR Digital Filters with Variable Frequency Characteristics," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 11, pp. 689-703, Nov. 2002.
13. S.C. Chan and W.L.K.L. Ho, "Multiplierless Perfect Reconstruction Modulated Filter Banks with Sum-of-Powers-of-Two Coefficients," Signal Processing Letters, IEE, vol. 8, no. 6, pp. 163-166, 2001.
14. V.S. Dimitrov, G.A. Jullien, and W.C. Miller, "Theory and Applications of the Double-Base Number System," IEEE Trans. Computers, vol. 48, no. 10, pp. 1098-1106, Oct. 1999.
15. J. Li and S. Tantaratana, "Multiplier-Free Realizations for FIR Multirate Converters Based on Mixed-Radix Number Representation," IEEE Trans. Signal Processing, vol. 45, no. 4, pp. 880-890, Apr. 1997.
16. N. Homma, T. Aoki, and T. Higuchi, "Evolutionary Graph Generation System with Transmigration Capability and Its Application to Arithmetic Circuit Synthesis," IEE Proc., vol. 149, no. 2, pp. 97-104, Apr. 2002.
17. P. Briggs and T. Harvey, "Multiplication by Integer Constants," technical report, Rice Univ., 1994.
18. M.F. Mellal and J.-M. Delosme, "Multiplier Optimization for Small Sets Of Coefficients," Proc. Int'l Workshop Logic and Architecture Synthesis, pp. 13-22, Dec. 1997.
19. H.T. Nguyen and A. Chatterjee, "Number-Splitting with Shift-and-Add Decomposition for Power and Hardware Optimization in Linear DSP Synthesis," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 8, no. 4, pp. 419-424, Aug. 2000.
20. H.-J. Kang and I.-C. Park, "FIR Filter Synthesis Algorithms for Minimizing the Delay and the Number of Adders," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 8, pp. 770-777, Aug. 2001.
21. M. Martínez-Peiró, E.I. Boemo, and L. Wanhammar, "Design of High-Speed Multiplierless Filters Using a Nonrecursive Signed Common Subexpression Algorithm," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 49, no. 3, pp. 196-203, Mar. 2002.
22. A. Vinod, E.-K. Lai, A. Premkumar, and C. Lau, "FIR Filter Implementation by Efficient Sharing of Horizontal and Vertical Common Subexpresions," Electronics Letters, vol. 39, no. 2, pp. 251-253, Jan. 2003.
23. A. Yurdakul and G. Dündar, "Fast and Efficient Algorithm for the Multiplierless Realisation of Linear DSP Transforms," IEE Proc. Circuits, Devices, and Systems, vol. 149, no. 4, pp. 20-211, Aug. 2002.
24. A. Matsuura, M. Yukishita, and A. Nagoya, "A Hierarchical Clustering Method for the Multiple Constant Multiplication Problem," IEICE Trans. Fundamentals of Electronics, Comm., and Computer Sciences, vol. E80-A, no. 10, pp. 1767-1773, Oct. 1997.
25. V. Lefèvre, "Multiplication par une Constante," Réseaux et Systèmes Répartis, Calculateurs Parallèles, vol. 13, nos. 4-5, pp. 465-484, 2001.
26. R. Paško, P. Schaumont, V. Derudder, S. Vernalde, and D. Ďuračková, "A New Algorithm for Elimination of Common Subexpressions," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 1, pp. 58-68, Jan. 1999.
27. A.G. Dempster, O. Gustafsson, and J.O. Coleman, "Towards an Algorithm for Matrix Multiplier Blocks," Proc. European Conf. Circuit Theory Design, Sept. 2003.
28. H. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Power-of-Two Coefficients," IEEE Trans. Circuits and Systems, vol. 36, no. 7, pp. 1044-1047, July 1989.