Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis

IEE Proceedings: Circuits, Devices and Systems

Volumn 149, Issue 2, 2002, Pages 97-104

  Homma, N ^a   Aoki, T ^a   Higuchi, T ^a  

^a TOHOKU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DATA FLOW ANALYSIS; DATA STRUCTURES; DIGITAL SIGNAL PROCESSING; ENCODING (SYMBOLS); EVOLUTIONARY ALGORITHMS; MULTIPLYING CIRCUITS; OPTIMIZATION; TREES (MATHEMATICS);

ARITHMETIC CIRCUIT SYNTHESIS; CANONIC SIGNED-DIGIT ENCODING; EVOLUTION PROCESS; EVOLUTIONARY GRAPH GENERATION SYSTEM; SIGNED-WEIGHT NUMBER SYSTEM; TRANSMIGRATION;

LOGIC DESIGN;

EID: 0036529342     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20020261     Document Type: Article

References (14)

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14. Constant integer multiplication using minimum adders