A hierarchical clustering method for the multiple constant multiplication problem

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E80-A, Issue 10, 1997, Pages 1767-1773

  Matsuura, Akihiro ^a   Yukishita, Mitsuteru ^a   Nagoya, Akira ^a  

^a NTT Communication Science Laboratories   (Japan)

Author keywords

Common subexpression; Constant multiplication; High level synthesis; MCM problem

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); COMPUTATIONAL METHODS; DIGITAL FILTERS; ERROR CORRECTION; MATHEMATICAL TRANSFORMATIONS;

DISCRETE COSINE TRANSFORMS; HIERARCHICAL CLUSTERING METHOD; HIGH LEVEL SYNTHESIS; MULTIPLE CONSTANT MULTIPLICATION PROBLEM;

LOGIC DESIGN;

EID: 0031247111     PISSN: 09168508     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. R. Jain, K. Kucukcakar, M.J. Milnar, and A.C. Parker, Experience with the ADAM synthesis system, ACM/IEEE Proc. 26th DAC, pp.56-61, 1989.
2. J.M. Rabaey, C. Chu, P. Hoang, and M. Potkonjak, Fast prototyping of datapath-intensive architectures, IEEE Design Test, pp.40-51, June 1991.
3. A. Nicolau and R. Potasman, Incremental tree height reduction for high level synthesis, ACM/IEEE Proc. 28th DAC, pp.770-774, 1991.
4. A. Chandrakasan, M. Potkonjak, J. Rabaey, and R.W. Brodersen, HYPER-LP: A system for power minimization using architectural transformations, Proc. ICCAD'92, pp.300-303, 1992.
5. A. Chatterjee and R.K. Roy, An architectural transformation program for optimization of digital systems by multi-level decomposition, ACM/IEEE Proc. 30th DAC, pp.343-348, 1993.
6. M. Potkonjak, M.B. Srivastava, and A.P. Chandrakasan, Efficient substitution of multiple constant multiplications by shifts and additions using iterative pairwise matching, I ACM/IEEE Proc. 31st DAC, pp.189-194, 1994.
7. M. Potkonjak, M.B. Srivastava, and A.P. Chandrakasan, Multiple constant triplications: Efficient and versatile framework and algorithms for exploring common subexpression elimination, IEEE Trans. Comput. -Aided Des. Integrated Circuits & Syst., vol.15, no.2, pp.151-165, Feb. 1996.
8. M. Mehendale, S.D. Shelekar, and G. Venkatesh, Synthesis of multiplier-less FIR filters with minimum number of additions, Proc. ICCAD'95, pp.668-671, 1995.
9. R. Bernstein, Multiplication by integer constants, Software - Practice and Experience, vol.16, no.7, pp.641-652, 1986.
10. D.J. Magenheimer, L. Peters, K. Pettis, and D. Zuras, Integer multiplication and division on the HP precision architecture, ASPLOS II, IEEE Computer Soc. Press, pp.9097, 1987.
11. F. Catthoor and H. de Man, SAMURAI: A general and efficient simulated annealing schedule with fully adaptive annealing parameters, Integration, vol.6, pp.147-178, 1988.
12. S. Roman, Coding and Information Theory, SpringerVerlag, Graduate Texts in Math., 1992.