메뉴 건너뛰기




Volumn , Issue , 2003, Pages 20-27

Some optimizations of hardware multiplication by constant matrices

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DISCRETE FOURIER TRANSFORMS; FIELD PROGRAMMABLE GATE ARRAYS; FIR FILTERS; SIGNAL PROCESSING; SIMULATED ANNEALING;

EID: 0043136418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (7)

References (19)
  • 1
    • 0022754418 scopus 로고
    • Multiplication by integer constants
    • July
    • R. Bernstein. Multiplication by integer constants. Software - Practice and Experience, 16(7):641-652, July 1986.
    • (1986) Software - Practice and Experience , vol.16 , Issue.7 , pp. 641-652
    • Bernstein, R.1
  • 2
    • 0036661353 scopus 로고    scopus 로고
    • FIR filters with punctured radix-8 symmetric coefficients: Design and multiplier-free realizations
    • P. Boonyanant and S. Tantaratana. FIR filters with punctured radix-8 symmetric coefficients: Design and multiplier-free realizations. Circuits Systems Signal Processing, 21(4):345-367, 2002.
    • (2002) Circuits Systems Signal Processing , vol.21 , Issue.4 , pp. 345-367
    • Boonyanant, P.1    Tantaratana, S.2
  • 3
    • 0001146101 scopus 로고
    • A signed binary multiplication technique
    • A. D. Booth. A signed binary multiplication technique. Quart. J. Mech. App. Math., IV(2):236-240, 1951.
    • (1951) Quart. J. Mech. App. Math. , vol.4 , Issue.2 , pp. 236-240
    • Booth, A.D.1
  • 4
    • 0042275094 scopus 로고
    • Multiplication by integer constants
    • Rice University
    • P. Briggs and T. Harvey. Multiplication by integer constants. Technical report, Rice University, 1994.
    • (1994) Technical Report
    • Briggs, P.1    Harvey, T.2
  • 5
    • 0002799279 scopus 로고
    • Fast integer multipliers fit in FPGAs
    • May
    • K. D. Chapman. Fast integer multipliers fit in FPGAs. EDN Magazine, May 1994.
    • (1994) EDN Magazine
    • Chapman, K.D.1
  • 8
    • 0036529342 scopus 로고    scopus 로고
    • Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis
    • Apr.
    • N. Homma, T. Aoki, and T. Higuchi. Evolutionary graph generation system with transmigration capability and its application to arithmetic circuit synthesis. IEE Proceedings, 149(2):97-104, Apr. 2002.
    • (2002) IEE Proceedings , vol.149 , Issue.2 , pp. 97-104
    • Homma, N.1    Aoki, T.2    Higuchi, T.3
  • 11
  • 15
    • 0034245054 scopus 로고    scopus 로고
    • Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis
    • Aug.
    • H. T. Nguyen and A. Chatterjee. Number-splitting with shift-and-add decomposition for power and hardware optimization in linear DSP synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 8(4):419-424, Aug. 2000.
    • (2000) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.8 , Issue.4 , pp. 419-424
    • Nguyen, H.T.1    Chatterjee, A.2
  • 18
    • 0024699067 scopus 로고
    • An improved search algorithm for the design of multiplierless FIR filters with power-of-two coefficients
    • July
    • H. Samueli. An improved search algorithm for the design of multiplierless FIR filters with power-of-two coefficients. IEEE Transactions on Circuits and Systems, 36(7): 1044-1047, July 1989.
    • (1989) IEEE Transactions on Circuits and Systems , vol.36 , Issue.7 , pp. 1044-1047
    • Samueli, H.1
  • 19
    • 0035439648 scopus 로고    scopus 로고
    • DCT implementation with distributed arithmetic
    • Sept.
    • S. Yu and E. E. Swartzlander. DCT implementation with distributed arithmetic. IEEE Transactions on Computers, 50(9):985-991, Sept. 2001.
    • (2001) IEEE Transactions on Computers , vol.50 , Issue.9 , pp. 985-991
    • Yu, S.1    Swartzlander, E.E.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.