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Volumn 3602, Issue , 2005, Pages 32-41

Trimaran: An infrastructure for research in instruction-level parallelism

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; CONTROL SYSTEMS; DATA REDUCTION; PARAMETER ESTIMATION; PROGRAM COMPILERS;

EID: 26444477602     PISSN: 03029743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1007/11532378_4     Document Type: Conference Paper
Times cited : (45)

References (32)
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    • Meld scheduling: A technique for relaxing scheduling constraints
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    • S. Abraham, V. Kathail, and B. Deitrich. Meld scheduling: A technique for relaxing scheduling constraints. Technical Report HPL-1997-39, Hewlett Packard Laboratories, Feb. 1997.
    • (1997) Technical Report , vol.HPL-1997-39
    • Abraham, S.1    Kathail, V.2    Deitrich, B.3
  • 8
    • 0003858279 scopus 로고    scopus 로고
    • Hmdes version 2.0 specification
    • University of Illinois, Urbana
    • J. Gyllenhaal, W. Hwu, and B. R. Rau. Hmdes version 2.0 specification. Technical Report IMPACT-96-3, University of Illinois, Urbana, 1996.
    • (1996) Technical Report , vol.IMPACT-96-3
    • Gyllenhaal, J.1    Hwu, W.2    Rau, B.R.3
  • 11
    • 84862452827 scopus 로고    scopus 로고
    • HPL-PD architecture specification: Version 1.1
    • (R.1), Hewlett Packard Laboratories, Feb.
    • V. Kathail, M. Schlansker, and B. R. Rau. HPL-PD architecture specification: Version 1.1. Technical Report HPL-9380 (R.1), Hewlett Packard Laboratories, Feb. 2000.
    • (2000) Technical Report , vol.HPL-9380
    • Kathail, V.1    Schlansker, M.2    Rau, B.R.3
  • 20
    • 0009755242 scopus 로고
    • Iterative modulo scheduling
    • Hewlett Packard Company, November
    • B. R. Rau. Iterative Modulo Scheduling. Technical Report HPL-94-115, Hewlett Packard Company, November 1995.
    • (1995) Technical Report , vol.HPL-94-115
    • Rau, B.R.1
  • 21
    • 0009755242 scopus 로고
    • Iterative modulo scheduling
    • Hewlett-Packard Laboratories, Nov.
    • B. R. Rau. Iterative modulo scheduling. Technical Report Technical Report HPL-94-115, Hewlett-Packard Laboratories, Nov. 1995.
    • (1995) Technical Report Technical Report , vol.HPL-94-115
    • Rau, B.R.1
  • 22
    • 26444513040 scopus 로고
    • Register allocation for modulo scheduled loops: Strategies, algorithms and heuristics
    • Hewlett Packard Laboratories, May
    • B. R. Rau, M. Lee, P. Tirumalai, and M. Schlansker. Register allocation for modulo scheduled loops: Strategies, algorithms and heuristics. Technical Report HPL-1992-48, Hewlett Packard Laboratories, May 1992.
    • (1992) Technical Report , vol.HPL-1992-48
    • Rau, B.R.1    Lee, M.2    Tirumalai, P.3    Schlansker, M.4
  • 24
    • 0033892359 scopus 로고    scopus 로고
    • EPIC: Explicitly Parallel Instruction Computing
    • M. Schlansker and B. Rau. EPIC: Explicitly Parallel Instruction Computing. IEEE Computer, 33(2):37-45, 2000.
    • (2000) IEEE Computer , vol.33 , Issue.2 , pp. 37-45
    • Schlansker, M.1    Rau, B.2
  • 28
    • 84861264969 scopus 로고    scopus 로고
    • STANDARD PERFORMANCE EVALUATION CORPORATION benchmark suite, http://www.spec.org.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.