Cache implications of aggressively pipelined high performance microprocessors

2004 IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2004, Pages 123-132

  Dysart, Timothy J ^a   Moore, Branden J ^a   Schaelicke, Lambert ^a   Kogge, Peter M ^a  

^a University of Notre Dame   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK RATES; PIPELINE DEPTHS; PIPELINED CACHES;

CLOCKS; COMPUTER SIMULATION; DATA REDUCTION; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SENSITIVITY ANALYSIS; SYSTEMS ANALYSIS;

CACHE MEMORY;

EID: 2642518138     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1109/ISPASS.2004.1291364     Document Type: Conference Paper

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