Challenges in implementing high-k dielectrics in the 45nm technology node

2005 International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2005, Pages 73-76

  Lee, B H ^b   Song, S C ^a   Choi, R ^a   Wen, H C ^a   Majhi, P ^c   Kirsch, P ^b   Young, C ^a   Bersuker, G ^a  

^a SEMATECH   (United States)

^b IBM   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE;

GATE STACK TECHNOLOGY;

DIELECTRIC DEVICES;

EID: 25844484118     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/icicdt.2005.1502595     Document Type: Conference Paper

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