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Volumn 3312, Issue , 2004, Pages 6-20

Generating fast multipliers using clever circuits

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FORMAL METHODS; RECONFIGURABLE HARDWARE; TREES (MATHEMATICS);

EID: 24944472073     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-30494-4_2     Document Type: Article
Times cited : (9)

References (15)
  • 1
    • 84961918328 scopus 로고    scopus 로고
    • An algorithmic approach to building datapath multipliers using (3,2) counters
    • IEEE Press, Apr.
    • H. Al-Twaijry and M. Aloqeely: An algorithmic approach to building datapath multipliers using (3,2) counters, IEEE Computer Society Workshop on VLSI, IEEE Press, Apr. 2000.
    • (2000) IEEE Computer Society Workshop on VLSI
    • Al-Twaijry, H.1    Aloqeely, M.2
  • 3
    • 0031190775 scopus 로고    scopus 로고
    • The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor
    • B. Brock and W. A. Hunt Jr.: The DUAL-EVAL Hardware Description Language and Its Use in the Formal Specification and Verification of the FM9001 Microprocessor. Formal Methods in System Design, 11(1), 1997.
    • (1997) Formal Methods in System Design , vol.11 , Issue.1
    • Brock, B.1    Hunt Jr., W.A.2
  • 5
    • 0001342967 scopus 로고
    • Some Schemes for Parallel Adders
    • May
    • L. Dadda: Some Schemes for Parallel Adders, Acta. Frequenza, vol. 34, no. 5, May 1965.
    • (1965) Acta. Frequenza , vol.34 , Issue.5
    • Dadda, L.1
  • 8
    • 0020929632 scopus 로고
    • Recursive Implementation of Optimal Time VLSI Integer Multipliers
    • Elsevier Science Publishes B.V. (North-Holland), Aug.
    • W. K. Luk and J. E. Vuillemin: Recursive Implementation of Optimal Time VLSI Integer Multipliers, VLSI'83, Elsevier Science Publishes B.V. (North-Holland), Aug. 1983.
    • (1983) VLSI'83
    • Luk, W.K.1    Vuillemin, J.E.2
  • 10
    • 0026907964 scopus 로고
    • "Overturned-Stairs" Adder Trees and Multiplier Design
    • Aug.
    • Z.-J. Mou and F. Jutand: "Overturned-Stairs" Adder Trees and Multiplier Design, IEEE Trans. on Computers, Vol. 41, No. 8, Aug. 1992.
    • (1992) IEEE Trans. on Computers , vol.41 , Issue.8
    • Mou, Z.-J.1    Jutand, F.2
  • 11
    • 17644373718 scopus 로고    scopus 로고
    • A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach
    • Mar.
    • V.G. Oklobdzija, D. Villeger and S.S. Liu: A Method for Speed Optimized Partial Product Reduction and Generation of Fast Parallel Multipliers Using an Algorithmic Approach. IEEE Trans. on Computers, vol. 45, no. 3, Mar. 1996.
    • (1996) IEEE Trans. on Computers , vol.45 , Issue.3
    • Oklobdzija, V.G.1    Villeger, D.2    Liu, S.S.3
  • 15
    • 84937739956 scopus 로고
    • A suggestion for a fast multiplier
    • Feb.
    • C. S. Wallace: A suggestion for a fast multiplier, IEEE Trans. on Computers, EC-13, 2, Feb. 1964.
    • (1964) IEEE Trans. on Computers , vol.EC-13 , Issue.2
    • Wallace, C.S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.