A regular parallel multiplier which utilizes multiple carry-propagate adders

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 166-169

  Eriksson, Heizrik ^a   Larsson Edefors, Per ^a   Marnane, William P ^b  

^a LINKÖPING UNIVERSITY   (Sweden)

^b UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

CARRY-PROPAGATION ADDERS; DELAY REDUCTION; GATE STRUCTURE; PARALLEL MULTIPLIERS; REDUCTION TREES;

FORESTRY;

ADDERS;

EID: 84888032456     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922198     Document Type: Conference Paper

References (8)

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