An algorithmic approach to building datapath multipliers using (3,2) counters

Proceedings - IEEE Computer Society Workshop on VLSI 2000: System Design for a System-on-Chip Era, IWV 2000

Volumn , Issue , 2000, Pages 135-139

  Al Twaijry, H ^a   Aloqeely, M ^a  

^a KING SAUD UNIVERSITY   (Saudi Arabia)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL ARITHMETIC;

ALGORITHMIC APPROACH; DATA PATHS; DEEP SUB-MICRON; DELAY MODELING; DELAY MODELS; IEEE FLOATING POINT;

ALGORITHMS;

EID: 84961918328     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2000.844542     Document Type: Conference Paper

References (14)

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