|
Volumn 5752, Issue II, 2005, Pages 727-735
|
Sampling plan optimization for CD control in low k1 lithography
|
Author keywords
ARC; CD control; CD SEM; Sampling plan; Scatterometry
|
Indexed keywords
CMOS INTEGRATED CIRCUITS;
ERROR ANALYSIS;
OPTIMIZATION;
PROCESS CONTROL;
STATISTICAL METHODS;
CRITICAL DIMENSION ERRORS;
DYNAMIC ERRORS;
STATISTICAL THEORY;
LITHOGRAPHY;
|
EID: 24644485283
PISSN: 16057422
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1117/12.600370 Document Type: Conference Paper |
Times cited : (5)
|
References (5)
|