OPC accuracy enhancement through systematic OPC calibration and verification methodology for sub-100nm node

Progress in Biomedical Optics and Imaging - Proceedings of SPIE

Volumn 5752, Issue II, 2005, Pages 720-726

  Yang, Hyunjo ^a   Choi, Jaeseung ^a   Cho, Byungug ^a   Cho, Byeongho ^a   Yim, Donggyu ^a   Kim, Jinwoong ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

CAD data; Graphic DRAMs; OPC accuracy; OPC calibration; OPC verification; RET

Indexed keywords

CALIBRATION; COMPUTER SIMULATION; IMAGE PROCESSING; MATHEMATICAL MODELS; OPTICAL RESOLVING POWER; SCANNING ELECTRON MICROSCOPY;

ISOLATED TRANSISTOR PATTERNS; OPC ACCURACY; OPC CALIBRATION; RESOLUTION ENHANCEMENT TECHNIQUES (RET);

DYNAMIC RANDOM ACCESS STORAGE;

EID: 24644483638     PISSN: 16057422     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.599728     Document Type: Conference Paper

References (5)

1. Kohji Hashimoto et al., Model-based PPC verification methodology with two-dimensional pattern feature extraction, Proc. of SPIE vol. 5040, 2003.
2. Ryoichi Matsuoka et al., New method for the quantitative evaluation of wafer pattern shape based on CAD data, Proc. of SPIE vol. 5038, 2003.
3. Ashesh Parikh et al., Quantification of OPC performance of 150-nm gates using top-down CD-SEM, Proc. of SPIE vol. 4689, 2002.
4. Kunal N. Taravade et al., Multichip reticle approach for OPC model verification, Proc. of SPIE vol. 5256, 2003.
5. Hyunjo Yang at al., OPC Accuracy and Process Window Verification Methodology for Sub-100nm Node, Proc. of SPIE vol. 5375, 2004