A scalable X86 CPU design for 90nm process

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Schutz, J ^a   Webb, C ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL BASED DESIGN; DIRECT ACCESS TESTING (DAT); END OF LIFE (EOL);

BUFFER STORAGE; FREQUENCIES; LEAKAGE CURRENTS; MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; OPTICAL INTERCONNECTS; ROUTERS; TRANSISTORS;

PROGRAM PROCESSORS;

EID: 2442667604     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. D. Sager et al., "A 0.18μm CMOS IA32 Microprocessor with a 4GHz Integer Execution Unit," ISSCC Dig. Tech. Papers, pp. 324-325, Feb. 2001.
2. D. Deleganes et al., "Designing a 3GHz, 130nm, Intel Pentium 4 Processor," Symp. VLSI Circuits Dig., pp. 130-133, Jun. 2002.
3. 2 Memory Bit," IEDM Tech. Dig., pp. 61-64, Dec. 2002.
4. S. Borkar, "Low-Power Design Challenges for the Decade," Proc. of ASP-DAC, pp. 293-296, Feb. 2001.
5. J. Davis et al., "Interconnect Limits in Gigascale Integration in the 21st Century," Proceedings of the IEEE, March 2001
6. D. D. Josephson, "The Manic Depression of Microprocessor Debug," Proc. of ITC Conf., pp. 657-663, Oct. 2002.
7. N. Bindal et al., "Scalable Sub-10ps Skew Global Clock Distribution for a 90nm Multi-Ghz IA Microprocessor," ISSCC Dig. Tech. Papers, pp. 346-347, Feb. 2003.
8. D. Deleganea et al., "Low-Voltage-Swing Logic Circuits for a 7GHz x86 Integer Core," ISSCC Dig. Tech. Papers, pp. 154, Feb. 2004.