A survey on IP watermarking techniques

Design Automation for Embedded Systems

Volumn 9, Issue 3, 2005, Pages 211-227

  Abdel Hamid, Amr T ^a   Tahar, Sofiéne ^a   Aboulhamid, El Mostapha ^b  

^a Dept of Electrical and Computer Engineering   (Canada)

^b UNIVERSITÉ DE MONTRÉAL   (Canada)

Author keywords

Copyright protection; Digital watermarking; Intellectual property protection; IP watermarking; System on a chip

Indexed keywords

COPYRIGHTS; DIGITAL WATERMARKING; EVALUATION; MICROPROCESSOR CHIPS;

COPYRIGHT PROTECTION; INTELLECTUAL PROPERTY PROTECTION; IP WATERMARKING; SYSTEM ON A CHIP;

INTELLECTUAL PROPERTY;

EID: 23944492659     PISSN: 09295585     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10617-005-1395-x     Document Type: Review

References (46)

1. Caldwell, A.E., H.J. Choi, A.B. Kahng, S. Mantik, M. Potkonjak, G. Qu, and J.L. Wong. Effective Iterative Techniques for Fingerprinting Design IP. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 2, pp. 208-215, 2004.
2. Cashwell, E.D. and C.J. Everett. A Practical Manual on the Monte Carlo Method for Random Walk Problems. Pergamon Press, 1959.
3. Chapman, R. and T.S. Durrani. IP Protection of DSP Algorithms for System on Chip Implementation. IEEE Transactions on Signal Processing, vol. 48, no. 3, pp. 854-861, 2000.
4. Charbon, E. Hierarchical Watermarking in IC Design. In Proc. IEEE Custom Integrated Circuits Conference, Santa Clara, California, USA, pp. 295-298, May 1998.
5. Charbon, E. and I. Torunoglu. Watermarking Layout Topologies. In Proc. IEEE Asia South-Pacific Design Automation Conference, Hong Kong, January 1999, pp. 213-216.
6. Charbon, E. and I. Torunoglu. Intellectual Property Protection Via Hierarchical Watermarking. In Proc. International Workshop on IP Based Synthesis and System Design, Grenoble, France, December 1998.
7. Cox, I.J., M.L. Miller, and J.A. Bloom. Digital Watermarking. Morgan Kaufmann Publishers, 1998.
8. Cravar, S. On Public-Key Steganography in the Presence of an Active Warden. Technical Report RC20931. IBM Research Division, T. J. Watson Research Center, July 1997.
9. Dalpasso, M., A. Bogliolo, and L. Benini. Virtual Simulation of Distributed IP-based Designs. In Proc. ACM/IEEE conference on Design Automation Conference, New Orleans, Louisiana, USA, June 1999, pp. 50-55.
10. Dalpasso, M., A. Bogliolo, and L. Benini. Hardware/Software IP Protection. In Proc. ACM/IEEE Design Automation Conference, Los Angeles, California, USA, June 2000, pp. 593-596.
11. Diffie, W. and M.E. Hellman. New Directions in Cryptography. IEEE Transactions on Information Theory, vol. 22, no. 6, pp. 644-654, 1976.
12. Fan, Y.C. and H.W. Tsao. Watermarking for Intellectual Property Protection. IEE Electronics Letters, vol. 39, no. 18, 2003.
13. Garey, M.R. and D.S. Johnson. Computers and Intractability - A Guide to the Theory of NP-Completeness. New York: W.H. Freeman And Company, 1979.
14. Hong, I. and M. Potkonjak. Techniques for Intellectual Property Protection of DSP Designs. In Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Munich, Germany, May 1998, vol. 5, pp. 3133-3136.
15. Intellectual Property Protection Development Working Group, Intellectual Property Protection: Schemes, Alternatives and Discussion. VSI Alliance, White Paper, Version 1.1, August 2001.
16. Kahng, A.B., D. Kirovski, S. Mantik, M. Potkonjak, and J.L. Wong. Copy Detection for Intellectual Property Protection of VLSI Design. In Proc. IEEE/ ACM International Conference on Computer-Aided Design, San Jose, California, USA, November 1999, pp. 600-604.
17. Kahng, A.B., J. Lach, W.H. Mangione-Smith, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe. Constraint-Based Watermarking Techniques for Design IP Protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 1236-1252, 2001.
18. Kahng, A.B., J. Lach, W.H. Mangione-Smith, S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe. Watermarking Techniques for Intellectual Property Protection. In Proc. ACM/IEEE Design Automation Conference, San Francico, California, USA, June 1998, pp. 776-781.
19. Kahng, A.B., S. Mantik, I.L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe. Robust IP Watermarking Methodologies for Physical Design. In Proc. ACM/IEEE Design Automation Conference, San Francico, California, USA, June 1998, pp. 782-787.
20. Kerckhoffs, A. La Cryptographie Militaire. Journal des sciences militaires, vol. IX, pp. 5-38, pp. 161-191, January 1883, February 1883.
21. Kirovski, D. and M. Potkonjak. Localized Watermarking: Methodology and Application to Template Mapping. In Proc. IEEE International Conference on Acoustics, Speech, and Signal Processing, Istanbul, Turkey, vol. 6, pp. 3235-3238, 2000.
22. Le-Van, T. and Y. Desmedt. Cryptanalysis of UCLA Watermarking Schemes for Intellectual Property Protection. In Information Hiding, LNCS 2578, Springer-Verilog, 2002, pp. 213-225.
23. Lach, J., W.H. Mangione-Smith, and M. Potkonjak. Fingerprinting Techniques for Field-Programmable Gate Array Intellectual Property Protection. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 10, pp. 831-836, 2001.
24. Lach, J., W.H. Mangione-Smith, and M. Potkonjak. Robust FPGA Intellectual Property Protection through Multiple Small Watermarks. In Proc. IEEE/ACM Design Automation Conference, New Orleans, Louisiana, USA, June 1999, pp. 831-836.
25. K. McElvain. LGSynth93 Benchmark Set: Version 4.0. http://www.cbl.ncsu.edu/pub/Benchmark.dirs/LGSynth93/, 1993.
26. Megerian, S., M. Drinic, and M. Potkonjak. Watermarking Integer Linear Programming Solutions. In Proc. IEEE/ACM Design Automation Conference, New Orleans, Louisiana, USA, June 2002, pp. 8-13.
27. Narayan, N., R.D. Newbould, J.D. Carothers, J.J. RodrIguez, and W. Timothy Holman. IP Protection for VLSI Designs Via Watermarking of Routes. In Proc. IEEE International ASIC/SOC Conference, Washington, DC, USA, September 2001, pp. 406-410.
28. Oliveira, A.L. Techniques for the Creation of Digital Watermarks in Sequential Circuit Designs. IEEE Transactions om Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1101-1117, 2001.
29. Petitcolas, F.A.F. Watermarking Schemes Evaluation. IEEE Magazine on Signal Processing, vol. 17, no. 5, pp. 58-64, 2000.
30. Petitcolas, F.A.P., R.J. Anderson, and M.G. Kuhn. Attacks on Copyright Marking Systems. In Information Hiding, LNCS 1525, Springer-Verlag, 1998, pp. 219-239.
31. Petitcolas, F.A.P., R.J. Anderson, and M.G. Kuhn. Information Hiding- A Survey. Proceeding of IEEE, vol. 87, no. 7, pp. 1062-1078, 1999.
32. Qu, G. Publicly Detectable Watermarking for Intellectual Property Authentication in VLSI Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 11, pp. 1363-1368, 2002.
33. Qu, G. and K. Potkonjak. Analysis of Watermarking Techniques for Graph Coloring Problem. In Proc. IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, USA, November 1998, pp. 190-193.
34. Qu, G. and M. Potkonjak. Fingerprinting Intellectual Property Using Constraint-Addition. In Proc. IEEE/ACM International Design Automation Conference, Los Angeles, California, USA, June 2000, pp. 587-592.
35. Qu, G., J.L. Wong, and M. Potkonjak. Fair Watermarking Techniques. In Proc. of Asian-Pacific Design Automation Conference, Yokohama, Japan, January 2000, pp. 55-60.
36. Rashid, A., J. Asher, W.H. Mangione-Smith, and M. Potkonjak. Heirarical Watermarking for Protection of DSP Filter Cores. In Proc. IEEE Custom Integrated Circuits Conferance, Orlando, Florida, USA, May 1999, pp. 39-42.
37. Rivest, R. RFC 1321: The MD5 Message-Digest Algorithm. Network Working Group, 1992.
38. Sentovich, E.M., K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, PR. Stephan, R.K. Brayton, and A. Sangiovanni-Vincentelli. SIS: A System for Sequential Circuit Synthesis. Technical Report, Dept. of Electrical Engineering and Computer Science, University of California, Berkeley, California, USA, 1992.
39. Simmons, G.J. The History of Subliminal Channels. IEEE Journal on Selected Areas in Communications, vol. 16, no. 4, pp. 452-462, 1998.
40. Simmons, G.J. Results Concerning the Bandwidth of Subliminal Channels. IEEE Journal on Selected Areas in Communications, vol. 16, no. 4, pp. 463-473, 1998.
41. Synopsys Inc., Verilog Model Compiler datasheet. http://www.synopsys.com/products/lm/ip/vmc.ds.html, 1999.
42. Torunoglu, I. and E. Charbon. Watermarking-Based Copyright Protection of Sequential Functions. IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 434-440, 2000.
43. Topdown Inc. TopProtect datasheet, 1999, http://www.topdown.com/topprotect/tp.dsheet.htm.
44. VSI Alliance. VSI Alliance Architecture Document: Version 1.0. VSI Alliance, 1997.
45. Wong, J.L., G. Qu, and M. Potkonjak. Optimization-Intensive Watermarking Techniques for Decision Problems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 119-125, 2004.
46. Wolfe, G., J.L. Wong, and M. Potkonjak. Watermarking Graph Partitioning Solutions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 21, no. 10, pp. 1196-2204, 2002.