Design and realisation of a new hardware efficient IP core for the 1-D discrete Fourier transform

IEE Proceedings: Circuits, Devices and Systems

Volumn 152, Issue 3, 2005, Pages 247-258

  Chien, C D ^a   Lin, C C ^a   Yang, C H ^a   Guo, J I ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; DISCRETE FOURIER TRANSFORMS; IMAGE PROCESSING; INTEGRATED CIRCUIT LAYOUT; INTELLECTUAL PROPERTY; MULTIMEDIA SYSTEMS; SIGNAL TO NOISE RATIO; VLSI CIRCUITS;

COMPUTATION COSTS; NON-TRIVIAL MULTIPLICATION; SYSTEM-ON-CHIP (SOC) DESIGN; WORD-LEVEL SHARING;

COMPUTER HARDWARE;

EID: 23744443049     PISSN: 13502409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1049/ip-cds:20041172     Document Type: Conference Paper

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