An efficient parallel adder based design for one dimensional discrete Fourier transform

Proceedings of the National Science Council, Republic of China, Part A: Physical Science and Engineering

Volumn 24, Issue 3, 2000, Pages 195-204

  Guo, J I ^a  

^a NATIONAL UNITED UNIVERSITY   (Taiwan)

Author keywords

Cyclic convolution; Discrete Fourier transform; Parallel adder based realization

Indexed keywords

ALGORITHMS; CONVOLUTION; FOURIER TRANSFORMS; Z TRANSFORMS;

DISCRETE FOURIER TRANSFORM; PARALLEL ADDER-BASED REALIZATION;

ADDERS;

FOURIER TRANSFORM;

EID: 0033888466     PISSN: 02556588     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (23)

1. A VLSI array for computing the DFT based on RNS
2. Efficient one-dimensional systolic array realization of discrete Fourier transform
3. A signed binary multiplication
4. A VLSI architecture for DFT
5. A new systolic array for discrete Fourier transform
6. Hardware efficient transform designs with cyclic convolution and subexpression sharing
7. Hardware-based Fourier transforms: Algorithms and architectures
8. An efficient unified systolic architecture for the computation of discrete trigonometric transforms
9. Computation of prime factor DFT and DHT/DCCT algorithms using cyclic and skew-cyclic bitserial semisystolic IC convolvers
10. An efficient parallel adder based design for the one dimensional discrete hartley transform
11. The efficient memory-based VLSI array designs for DFT and DCT
12. Comparison of single and dual pass multiply-add fused floating-point units
13. A fully pipelined, high speed DFT architecture
14. Special purpose devices for signal and image processing: An opportunity in very large scale integration (VLSI)
15. Why systolic architectures?
16. A new systolic array algorithm for discrete Fourier transform
17. On the real-time computation of DFT and DCT through systolic architectures
18. A proof of the modified booth algorithm for multiplication
19. A new systolic architecture for pipeline prime factor DFT algorithm
20. Fourier transforms in VLSI
21. A novel double decomposition method for systolic implementation of DFT
22. Applications of distributed arithmetic to digital signal processing: A tutorial review