Enhancing SAT-based bounded model checking using sequential logic implications

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 784-787

  Arora, Rajat ^a   Hsiao, Michael S ^a  

^a Virginia Polytechnic Institute and State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDED MODEL CHECKING (BMC); CIRCUIT UNDER VERIFICATION (CUV); MONITOR CIRCUITS; STATIC LOGIC IMPLICATIONS;

APPROXIMATION THEORY; DECISION MAKING; GRAPH THEORY; LOGIC DEVICES; PERFORMANCE; SIGNAL PROCESSING;

COMPUTER SCIENCE;

EID: 2342655036     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (17)

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