A graph traversal based framework for sequential logic implication with an application to c-cycle redundancy identification

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2001, Pages 163-169

  Zhao, Jian Kun ^a   Newquist, Jeffrey A ^a   Patel, Janak H ^a  

^a University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; GRAPH THEORY; ITERATIVE METHODS; REDUNDANCY;

GRAPH TRAVERSAL; REDUNDANT FAULT IDENTIFICATION;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 0035016402     PISSN: 10639667     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICVD.2001.902656     Document Type: Article

References (0)