Learning from BDDs in SAT-based bounded model checking

Proceedings - Design Automation Conference

Volumn , Issue , 2003, Pages 824-829

  Gupta, Aarti ^a   Ganai, Malay ^a   Wang, Chao ^b   Yang, Zijiang ^a   Ashar, Pranav ^a  

^a NEC LABORATORIES AMERICA   (United States)

^b UCB 450   (United States)

Author keywords

BDD learning; BDDs; Boolean Satisfiability; Bounded model checking; Learning; Property checking; SAT; SAT solvers

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; DECISION THEORY; HEURISTIC METHODS; LEARNING SYSTEMS; MATHEMATICAL MODELS;

SYSTEM VERIFICATIONS;

SYSTEMS ANALYSIS;

EID: 0042635589     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/776038.776040     Document Type: Conference Paper

References (25)

1. E. M. Clarke, O. Grumberg, and D. Peled, Model Checking: MIT Press, 1999.
2. K. L. McMillan, Symbolic Model Checking: An Approach to the State Explosion Problem: Kluwer Academic Publishers, 1993.
3. R. E. Bryant, "Graph-based algorithms for Boolean function manipulation," IEEE Transactions on Computers, vol. C-35(8), pp. 677-691, 1986.
4. A. Biere, A. Cimatti, E. M. Clarke, and Y. Zhu, "Symbolic Model Checking without BDDs," in Proceedings of Workshop on Tools and Algorithms for Analysis and Construction of Systems (TACAS), vol. 1579, LNCS, 1999.
5. J. P. Marques-Silva and K. A. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability," IEEE Transactions on Computers, vol. 48, pp. 506-521, 1999.
6. H. Zhang, "SATO: An efficient prepositional prover," in Proceedings of International Conference on Automated Deduction, vol. 1249, LNAI, 1997, pp. 272-275.
7. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in Proceedings of Design Automation Conference, 2001.
8. E. Goldberg and Y. Novikov, "BerkMin: A Fast and Robust SAT-Solver," in Proceedings of Conference on Design Automation and Test Europe (DATE), 2002, pp. 142-149.
9. O. Strichman, "Pruning Techniques for the SAT-based bounded model checking," in Proceedings of Workshop on Tools and Algorithms for the Analysis and Construction of Systems (TACAS), 2001.
10. G. Anderson, P. Bjesse, B. Cook, and Z. Hanna, "A Proof Engine Approach to Solving Combinational Design Automation Problems," in Proceedings of the DAC, 2002.
11. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design: Computer Science Press, 1990.
12. J. Jain, R. Mukherjee, and M. Fujita, "Advanced Verification Techniques based on Learning," in Proceedings of the Design Automation Conference, 1995.
13. W. Kunz, D. Pradhan, and S. M. Reddy, "A Novel Framework for Logic Verification in a Synthesis Environment," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 20-32, 1996.
14. A. Gupta and P. Ashar, "Integrating a Boolean Satisfiability Checker and BDDs for Combinational Verification," in Proceedings of the VLSI Design Conference, 1998.
15. J. R. Burch and V. Singhal, "Tight integration of combinational verification methods," in Proceedings of International Conference on Computer-Aided Design, 1998.
16. A. Kuehlmann, M. Ganai, and V. Paruthi, "Circuit-based Boolean Reasoning," in Proceedings of Design Automation Conference, 2001.
17. A. Gupta, Z. Yang, P. Ashar, and A. Gupta, "SAT-based Image Computation with Application in Reachability Analysis," in Proceedings of Conference on Formal Methods in Computer-Aided Design, 2000, pp. 354-371.
18. P. Williams, A. Biere, E. M. Clarke, and A. Gupta, "Combining Decision Diagrams and SAT Procedures for Efficient Symbolic Model Checking," in Proceedings of International Conference on Computer-Aided Verification, vol. 1855, LNCS, 2000, pp. 124-138.
19. P. A. Abdulla, P. Bjesse, and N. Een, "Symbolic Reachability Analysis based on SAT-Solvers," in Proceedings of Workshop on Tools and Algorithms for the Analysis and Construction of Systems (TACAS), 2000.
20. A. Kuehlmann and F. Krohm, "Equivalence Checking using Cuts and Heaps," in Proceedings of DAC, 1997.
21. M. Davis, G. Longeman, and D. Loveland, "A Machine Program for Theorem Proving," Communications of the ACM, vol. 5, pp. 394-397, 1962.
22. J. Pilarski and G. Hu, "SAT with Partial Clauses and Back-Leaps," in Proceedings of DAC, 2002, pp. 743-746.
23. F. Somenzi, "CUDD: University of Colorado Decision Diagram Package, http://vlsi.colorado.edu/̃fabio/CUDD/," 1998.
24. M. Ganai, L. Zhang, P. Ashar, and A. Gupta, "Combining Strengths of Circuit-based and CNF-based Algorithms for a High Performance SAT Solver," in Proceedings of the Design Automation Conference, 2002.
25. R. Brayton, F. Somenzi, and others, "VIS: Verification Interacting with Synthesis, http://vlsi.colorado.edu/̃vis," 2002.