Exploring the novel characteristics of fully depleted dual-material gate (DMG) SOI MOSFET using two-dimensional numerical simulation studies

Proceedings of the IEEE International Conference on VLSI Design

Volumn 17, Issue , 2004, Pages 662-665

  Chaudhry, Anurag ^a   Kumar, M Jagadesh ^a  

^a INDIAN INSTITUTE OF TECHNOLOGY DELHI   (India)

Author keywords

[No Author keywords available]

Indexed keywords

DUAL MATERIAL GATE (DMG); SHORT-CHANNEL EFFECTS (SCE); SINGLE MATERIAL GATE (SMG); WORKFUNCTIONS;

COMPUTER SIMULATION; FUNCTIONS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; MASKS; MOS CAPACITORS; THRESHOLD VOLTAGE; VECTORS;

MOSFET DEVICES;

EID: 2342588638     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. R. H. Dennard, et al., "Design of ion-implanted MOSFET's with very small physical dimensions," IEEE J. Solid-State Circuits, vol. SC-9, pp.256-268, 1974.
2. P. K. Vasudev, "Ultra-thin silicon-on-insulator for high speed submicrometer CMOS technology," Solid State Technol. pp. 61-65, 1990.
3. T. Ushiki, et al., "Reliable Tantalum-Gate fully depleted SOI MOSFET technology featuring low-temperature processing," IEEE Trans. Electron Devices, vol. 44, pp 1467-1472, 1997.
4. I. Sekigawa and Y. Hayashi, "Calculated threshold voltage characteristics of an XMOS transistor having an additional bottom gate," Solid-State Electronics, Vol. 27, No. 8-9, pp. 827-828, 1984.
5. N. Lindert, et al., "Sub-60-nm quasiplanar FinFET's fabricated using a simplified process," IEEE Electron Device Lett., vol. 22, pp. 487-489, 2001.
6. W. Long, et al., "Dual material gate (DMG) field effect transistor," IEEE Trans. Electron Devices, vol. 46, pp.865-870, 1999.
7. MEDICI 4.0, Technology Modeling Associates, Inc., Palo Alto, CA, 1997.
8. X. Zhou, et al., "A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling," IEEE Trans. Electron Devices, vol. 46, pp. 807-809, 1999.
9. A. Hiroki, et al., "A high performance 0.1 urn MOSFET with asymmetric channel profile," in IEDM Tech. Dig., 1995, pp. 439-442.
10. X. Zhou, "Exploring the novel characteristics of Hetero-Material Gate Field-Effect transistors (HMGFET's) with gate-material engineering," IEEE Trans. Electron Devices, vol. 47, pp.113-120, 2000.
11. J. Hergenrother et al., "The vertical replacement-gate (VRG) MOSFET: A 50-nm vertical MOSFET with lithography-independent gate length," pp 75-79, IEDM Tech. Dig., 1999.