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Volumn 2003-January, Issue , 2003, Pages 518-522

Effect of programming biases on the reliability of CHE and CHISEL flash EEPROMs

Author keywords

CHE; CHISEL; Cycling endurance and Monte Carlo simulation; Flash EEPROM; Hot carriers

Indexed keywords

FLASH MEMORY; HOT CARRIERS; INTELLIGENT SYSTEMS; RELIABILITY; TOOLS;

EID: 2342571991     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2003.1197802     Document Type: Conference Paper
Times cited : (3)

References (9)
  • 1
    • 0038781584 scopus 로고    scopus 로고
    • Multilevel flash memories
    • Kluwer Academic Publishers, Boston MA
    • G. Torelli, M. Lanzoni, A. Manstratta and B. Rico, "Multilevel flash memories", in Flash Memories, pp. 361, Kluwer Academic Publishers, Boston MA, 1999.
    • (1999) Flash Memories , pp. 361
    • Torelli, G.1    Lanzoni, M.2    Manstratta, A.3    Rico, B.4
  • 4
    • 0029516230 scopus 로고
    • EEPROM/flash sub-3.0V drain-source bias hot carrier writing
    • J. D. Bude, A. Frommer, M. R. Pinto and G. R. Weber, "EEPROM/flash sub-3.0V drain-source bias hot carrier writing", in IEDM Tech. Digest, pp. 989, 1995.
    • (1995) IEDM Tech. Digest , pp. 989
    • Bude, J.D.1    Frommer, A.2    Pinto, M.R.3    Weber, G.R.4
  • 7
    • 0033190189 scopus 로고    scopus 로고
    • Low voltage flash memory by use of a substrate bias
    • M. Mastrapasqua, "Low voltage flash memory by use of a substrate bias", Microelectronics Engineering, Vol. 48, pp. 389, 1999.
    • (1999) Microelectronics Engineering , vol.48 , pp. 389
    • Mastrapasqua, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.