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Volumn 17, Issue , 2004, Pages 443-448

A bus encoding technique for power and cross-talk minimization

Author keywords

Cross talk; Encoding techniques; Limited Weight Codes; Low Power Design; Memoryless bus encoding; Pipelining.; Transition Signalling

Indexed keywords

ALGORITHMS; BUSBARS; CROSSTALK; DECODING; ELECTRIC POWER SUPPLIES TO APPARATUS; ENGINEERING RESEARCH; GATES (TRANSISTOR); LOGIC DESIGN;

EID: 2342450522     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (42)

References (15)
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    • Benini, L.1    Micheli, G.D.2    Maci, E.3    Sciut, D.4    Silvano, C.5
  • 2
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    • J.Henkel and H.Lekatsas. "A2BC: Adaptive Address Bus Coding for Low-Power Deep Sub-Micron Designs". In Design Automation Conference (DAC 2001), Las Vegas, Nevada, 2001.
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    • Henkel, J.1    Lekatsas, H.2
  • 4
    • 0029776652 scopus 로고    scopus 로고
    • Reducing address bus transitions for low power memory mapping
    • Paris, France, March
    • P.R.Panda and N.D.Dutt. "Reducing Address Bus Transitions for Low Power Memory Mapping". In EDTC-96:IEEE European Design and Test Conference, pages 63-67, Paris, France, March 1996.
    • (1996) EDTC-96:IEEE European Design and Test Conference , pp. 63-67
    • Panda, P.R.1    Dutt, N.D.2
  • 6
    • 0032646416 scopus 로고    scopus 로고
    • Information-theoretic bounds on average signal transition activity
    • September
    • S. Ramprasad, N.R. Shanbhag, and I.N. Hajj. "Information-theoretic Bounds on Average Signal Transition Activity". IEEE Transactions on VLSI Systems, 7(3):359-368, September 1999.
    • (1999) IEEE Transactions on VLSI Systems , vol.7 , Issue.3 , pp. 359-368
    • Ramprasad, S.1    Shanbhag, N.R.2    Hajj, I.N.3
  • 7
    • 0035301452 scopus 로고    scopus 로고
    • Partial bus- Invert coding for power optimization of application specific systems
    • April
    • Y.Shin, S.Chae, and K. Choi. "Partial Bus- Invert Coding for Power Optimization of Application Specific Systems". IEEE Transactions on VLSI Systems, 9(2):377-383, April 2001.
    • (2001) IEEE Transactions on VLSI Systems , vol.9 , Issue.2 , pp. 377-383
    • Shin, Y.1    Chae, S.2    Choi, K.3
  • 10
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    • Bus-invert coding for low power I/O
    • March
    • M.R. Stan and W.P. Burleson. "Bus-Invert Coding for Low Power I/O". In IEEE Transactions on VLSI, volume 3, pages 49-59, March 1995.
    • (1995) IEEE Transactions on VLSI , vol.3 , pp. 49-59
    • Stan, M.R.1    Burleson, W.P.2
  • 12
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    • Bus encoding to prevent cross-talk delay
    • San Jose, CA, November 4-8
    • Bret Victor and Kurt Keutzer. "Bus Encoding to Prevent Cross-Talk Delay". In Proc. of ICCAD 2001, pages 57-64, San Jose, CA, November 4-8 2001.
    • (2001) Proc. of ICCAD 2001 , pp. 57-64
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  • 15


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.