Strategies for simulation, measurement and suppression of digital noise in mixed-signal circuits

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 361-364

  Owens, Brian ^a   Birrer, Patrick ^a   Adluri, Sirisha ^a   Shreeve, Robert ^a   Kumar Arunachalam, Sasi ^a   Habal, Husni ^a   Hsu, Shuching ^a   Sharma, Ajit ^a   Mayaram, Kartikeya ^a   Fiez, Terri S ^a  

^a Oregon State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; INDUCTANCE; MOSFET DEVICES; SPURIOUS SIGNAL NOISE; SUBSTRATES;

DIGITAL NOISE GENERATOR; LUMPED RESISTIVE NETWORK; MIXED-SIGNAL CIRCUIT; NOISE SUPPRESSION TECHNIQUE;

SIGNAL GENERATORS;

EID: 0242696113     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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