-
1
-
-
0030110592
-
Modeling and analysis of substrate coupling in integrated circuits
-
Mar.
-
R. Gharpurey and R.G. Meyer, "Modeling and Analysis of Substrate Coupling in Integrated Circuits," IEEE Journal of Solid-State Circuits, vol. 31, pp. 344-353, Mar. 1996.
-
(1996)
IEEE Journal of Solid-State Circuits
, vol.31
, pp. 344-353
-
-
Gharpurey, R.1
Meyer, R.G.2
-
2
-
-
0003653510
-
Simulation techniques and solutions for mixed-signal coupling in ICs
-
Boston Kluwer Academic Publishers
-
N.K. Verghese, T. Schmerbeck, and D.J. Allstot, Simulation techniques and solutions for mixed-signal coupling in ICs. Boston: Kluwer Academic Publishers, 1995.
-
(1995)
-
-
Verghese, N.K.1
Schmerbeck, T.2
Allstot, D.J.3
-
3
-
-
0032597766
-
A review of substrate coupling issues and modeling strategies
-
May
-
R. Singh, "A Review of Substrate Coupling Issues and Modeling Strategies," in Proc. CICC, pp. 491-498, May 1999.
-
(1999)
Proc. CICC
, pp. 491-498
-
-
Singh, R.1
-
4
-
-
0027929105
-
LAYIN: Toward a global solution for parasitic coupling modeling and visualization
-
May
-
F.J.R. Clement, E. Zysman, M. Kayal, and M. Declercq, "LAYIN: Toward a global solution for parasitic coupling modeling and visualization," in Proc. IEEE Custom Integrated Circuits Conference, pp. 537 - 540, May 1994.
-
(1994)
Proc. IEEE Custom Integrated Circuits Conference
, pp. 537-540
-
-
Clement, F.J.R.1
Zysman, E.2
Kayal, M.3
Declercq, M.4
-
5
-
-
0029518880
-
Stable and efficient reduction of substrate model networks using congruence transforms
-
K.J. Kerns, I.L. Wemple, and A.T. Yang, "Stable and Efficient Reduction of Substrate Model Networks Using Congruence Transforms," in Proceedings DAC, pp. 207 - 214, 1995.
-
(1995)
Proceedings DAC
, pp. 207-214
-
-
Kerns, K.J.1
Wemple, I.L.2
Yang, A.T.3
-
6
-
-
0003562387
-
Analysis and solutions for switching noise coupling in mixed-signal ICs
-
Boston: Kluwer Academic Publishers
-
X. Aragones, J.L. Gonzalez, and A. Rubio, Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs. Boston: Kluwer Academic Publishers, 1999.
-
(1999)
-
-
Aragones, X.1
Gonzalez, J.L.2
Rubio, A.3
-
7
-
-
0029723722
-
SubWave: A methodology for modeling digital substrate noise in mixed-signal IC's
-
P. Miliozzi, L. Carloni, E. Charbon, and A. Sangiovanni-Vincentelli, "SubWave: a Methodology for Modeling Digital Substrate Noise in Mixed-Signal IC's," in Proceedings IEEE CICC, pp. 385 - 38, 1996.
-
(1996)
Proceedings IEEE CICC
, pp. 385-388
-
-
Miliozzi, P.1
Carloni, L.2
Charbon, E.3
Sangiovanni-Vincentelli, A.4
-
8
-
-
0030270723
-
Modeling substrate effects in the design of high-speed si-bipolar IC's
-
Oct.
-
M. Pfost, H.M. Rein, and T. Holzwarth, "Modeling Substrate Effects in the Design of High-Speed Si-Bipolar IC's," IEEE Journal on Solid-State Circuits, vol. 31, pp. 1493 - 1501, Oct. 1996.
-
(1996)
IEEE Journal on Solid-State Circuits
, vol.31
, pp. 1493-1501
-
-
Pfost, M.1
Rein, H.M.2
Holzwarth, T.3
-
9
-
-
0027576336
-
Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits
-
Apr.
-
D.K. Su, M.J. Loinaz, S. Masui, and B.A. Wooley, "Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits," IEEE Journal of Solid-State Electronics, vol. 28, pp. 420-430, Apr. 1993.
-
(1993)
IEEE Journal of Solid-State Electronics
, vol.28
, pp. 420-430
-
-
Su, D.K.1
Loinaz, M.J.2
Masui, S.3
Wooley, B.A.4
-
10
-
-
0029487138
-
Extraction of circuit models for substrate cross-talk
-
Nov.
-
T. Smedes, N. P. van der Meijs, and A. J. van Genderen, "Extraction of Circuit Models for Substrate Cross-talk," in Proc. Int. Conf. on Computer-Aided Design, (San Jose, California), pp. 199-206, Nov. 1995.
-
(1995)
Proc. Int. Conf. on Computer-Aided Design, (San Jose, California)
, pp. 199-206
-
-
Smedes, T.1
Van Der Meijs, N.P.2
Van Genderen, A.J.3
-
11
-
-
0036051248
-
Combined BEM/FEM substrate resistance modeling
-
(New Orleans, LA); June
-
E. Schrik and N.P. van der Meijs, "Combined BEM/FEM Substrate Resistance Modeling," in Proceedings DAC 2002, (New Orleans, LA) pp. 771 - 776, June 2002.
-
(2002)
Proceedings DAC 2002
, pp. 771-776
-
-
Schrik, E.1
Van Der Meijs, N.P.2
-
13
-
-
84939344864
-
SPIDER - A CAD system for modeling VLSI metallization patterns
-
Nov.
-
J.E. Hall, D.E. Hocevar, P. Yang, and M.M. McGraw, "SPIDER - A CAD System for Modeling VLSI Metallization Patterns," IEEE Transactions on CAD, vol. 6, pp. 1023 - 1031, Nov. 1987.
-
(1987)
IEEE Transactions on CAD
, vol.6
, pp. 1023-1031
-
-
Hall, J.E.1
Hocevar, D.E.2
Yang, P.3
McGraw, M.M.4
-
17
-
-
0012146396
-
A hybrid element method for calculation of capacitances from the layout of integrated circuits
-
(R. C. Ertekin, C. A. Brebbia, M. Tanak, and R. Shaw, eds.), (Hawai, U.S.A.); Computational Mechanics Publications, May
-
E. B. Nowacka, P. Dewilde, and T. Smedes, "A Hybrid Element Method for Calculation of Capacitances from the Layout of Integrated Circuits," in Boundary Element Technology XI (Proc BETECH 96) (R. C. Ertekin, C. A. Brebbia, M. Tanak, and R. Shaw, eds.), (Hawai, U.S.A.), pp. 415-425, Computational Mechanics Publications, May 1996.
-
(1996)
Boundary Element Technology XI (Proc BETECH 96)
, pp. 415-425
-
-
Nowacka, E.B.1
Dewilde, P.2
Smedes, T.3
-
18
-
-
0001772648
-
Deep-submicron ULSI parasitics extraction using space
-
Feb.
-
F. Beeftink, A.J. van Genderen, N.P. van der Meijs, and J. Poltz, "Deep-Submicron ULSI Parasitics Extraction Using Space," in Design, Automation and Test in Europe Conference 1998, Designer Track, pp. 81-86, Feb. 1998.
-
(1998)
Design, Automation and Test in Europe Conference 1998, Designer Track
, pp. 81-86
-
-
Beeftink, F.1
Van Genderen, A.J.2
Van Der Meijs, N.P.3
Poltz, J.4
-
19
-
-
0012186043
-
A 2.5 D EM simulator by agilent EEsof
-
Momentum
-
Momentum, a 2.5 D EM Simulator by Agilent EEsof, see http://eesof.tm.agilent.com.
-
-
-
-
20
-
-
0012110265
-
A 3D device simulator by synopsys
-
Davinci (Taurus)
-
Davinci (Taurus), a 3D Device simulator by Synopsys, see http://www.synopsys.com.
-
-
-
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