Compliant stress-engineered interconnects for-next generation packaging

American Society of Mechanical Engineers, Electronic and Photonic Packaging, EPP

Volumn 4, Issue , 2004, Pages 219-226

  Klein, Kevin M ^a   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Compliant interconnects; Copper; Intrinsic stress; Optimization; Regression modeling

Indexed keywords

COEFFICIENT OF THERMAL EXPANSION (CTE); COMPLAINT INTERCONNECTS; INTRINSIC STRESS; REGRESSION MODELING;

COMPUTER SIMULATION; COPPER; COSTS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; OPTIMIZATION; REGRESSION ANALYSIS; SEMICONDUCTOR MATERIALS; SILICON WAFERS; STRESS ANALYSIS; THERMAL EXPANSION;

INTERCONNECTION NETWORKS;

EID: 23244434201     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IMECE2004-61990     Document Type: Conference Paper

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