Estimation of wafer warpage profile during thermal processing in microlithography

Review of Scientific Instruments

Volumn 76, Issue 7, 2005, Pages

  Tay, Arthur ^a   Ho, Weng Khuen ^a   Hu, Ni ^a   Chen, Xiaoqi ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b SINGAPORE INSTITUTE OF MANUFACTURING TECHNOLOGY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL DIMENSION (CD); SEMICONDUCTOR WAFERS; THERMAL PROCESSING; WAFER WARPAGE;

COST EFFECTIVENESS; ELECTRIC RESISTANCE; LITHOGRAPHY; MICROELECTRONICS; RELIABILITY; SEMICONDUCTOR MATERIALS;

SILICON WAFERS;

COST EFFECTIVENESS; LITHOGRAPHY; PARTICLE BOARDS; RELIABILITY; SEMICONDUCTORS; THERMAL RESISTANCE; WARPAGE;

EID: 22944434184     PISSN: 00346748     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1979468     Document Type: Article

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