Fully planar 0.562μm 2 T-RAM cell in a 130nm SOI CMOS logic technology for high-density high-performance SRAMs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 273-274

  Nemati, Farid ^a   Cho, Hyun Jin ^a   Robins, Scott ^a   Gupta, Rajesh ^a   Tarabbia, Marc ^a   Yang, Kevin J ^a   Hayes, Dennis ^a   Gopalakrishnan, Vasudevan ^a  

^a T RAM Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELL DATA; CELL TECHNOLOGY; COUPLED GATES; CROSS-SECTIONS; 'CURRENT; CELL-BE; CELL/B.E; CELL/BE; CMOS LOGIC; LOGIC TECHNOLOGY; MANUFACTURABILITY; PERFORMANCE; PHOTO MASK; SOI CMOS;

CAPACITORS; CMOS INTEGRATED CIRCUITS; ION IMPLANTATION; MASKS; PERFORMANCE; TECHNOLOGY; THERMODYNAMIC STABILITY; THYRISTORS; COMPUTER CIRCUITS;

STATIC RANDOM ACCESS STORAGE; CMOS INTEGRATED CIRCUITS;

EID: 21644448083     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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