45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 8-9

  Yang, Fu Liang ^a   Huang, Cheng Chuan ^a   Huang, Chien Chao ^a   Chung, Tang Xuan ^a   Chen, Hou Yu ^a   Chang, Chang Yun ^a   Chen, Hung Wei ^a   Lee, Di Hong ^a   Liu, Sheng Da ^a   Chen, Kuang Hsin ^a   Wen, Cheng Kuo ^a   Cheng, Shui Ming ^a   Yang, Chang Ta ^a   Kung, Li Wei ^a   Lee, Chiu Lien ^a   Chou, Yu Jun ^a   Liang, Fu Jye ^a   Shiu, Lin Hung ^a   You, Jan Wen ^a   Shu, King Chang ^a   Chang, Bin Chang ^a   Shin, Jaw Jung ^a   Chen, Chun Kuang ^a   Gau, Tsai Sheng ^a   Wang, Ping Wei ^a   Chan, Bor Wen ^a   Hsu, Peng Fu ^a   Shieh, Jyu Horng ^a   Fung, Samuel K H ^a   Diaz, Carlos H ^a   Wu, Chii Ming M ^a   See, Yee Chaung ^a   Lin, Bum J ^a   Liang, Mong Song ^a   Sun, Jack Y C ^a   Hu, Chenming ^a   more..

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; LITHOGRAPHY; POLYSILICON; SCANNING ELECTRON MICROSCOPY; SPURIOUS SIGNAL NOISE; STATIC RANDOM ACCESS STORAGE; TECHNOLOGY;

CELL SIZE REDUCTION; DRAIN JUNCTIONS; GATE LENGTHS; POLY ETCHING;

SILICON ON INSULATOR TECHNOLOGY;

EID: 4544294969     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. F. Arnaud et al., Symp. on VLSI Technology 2003, pp. 65.
2. M. Kanda et al., Symp. on VLSI Technology 2003, pp. 13.
3. F.-L. Yang et al., IEDM 2003, pp. 627.
4. C.-H. Ge et al., IEDM 2003, pp. 73.
5. F.-L. Yang et al., Symp. on VLSI Technology 2003, pp. 137.
6. S. K. H. Fung et al., IEDM 2001. pp. 629.
7. K. Goto et al., IEDM 2003, pp. 623.
8. E. Morifuji et al., IEDM 2002, pp. 655.