Edge trapping mechanism of current collapse in III-N FETs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 815-818

  Braga, N ^a   Mickevicius, R ^a   Gaska, R ^b   Shur, M S ^c   Khan, M Asif ^d   Simin, G ^d  

^a Integrated Systems Inc   (United States)

^b SENSOR ELECTRONIC TECHNOLOGY INC   (United States)

^c RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^d University of South Carolina   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONDUCTION BANDS; DEVICE STRUCTURE; DRAIN CURRENTS; PINCH-OFF VOLTAGE; % REDUCTIONS; CURRENT COLLAPSE; DEVICE SIMULATORS; GAN HFET; GATE EDGE; TRANSMISSION-LINE MEASUREMENTS; TRAPPING MECHANISMS;

COMPUTER SIMULATION; DIFFUSION; ELECTRIC CURRENTS; ELECTRIC LINES; ELECTRIC POTENTIAL; ELECTRIC RESISTANCE; GALLIUM NITRIDE; MATHEMATICAL MODELS; NITRIDES; PYROELECTRICITY; RELAXATION PROCESSES; SEMICONDUCTING ALUMINUM COMPOUNDS; HOT ELECTRONS; III-V SEMICONDUCTORS; SEMICONDUCTOR ALLOYS;

FIELD EFFECT TRANSISTORS; ELECTRIC CURRENT MEASUREMENT;

EID: 21644446415     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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