Fabrication and characterization of 1 k-bit 1T2C-type ferroelectric memory cell array

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 44, Issue 4 B, 2005, Pages 2715-2721

  Kim, Hyun Soo ^b   Yamamoto, Shuu'ichirou ^b   Ishikawa, Toru ^a   Fuchikami, Takaaki ^a   Ohki, Hiroshi ^a   Ishiwara, Hiroshi ^b  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^b R and D Association for Future Electron Device   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA REDUCTION; FERROELECTRIC DEVICES; FIELD EFFECT TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; NONDESTRUCTIVE EXAMINATION; READOUT SYSTEMS;

1T2C-TYPE FERROELECTRIC MEMORY; DATA DISTURBANCE; DATA RETENTION; FERROELECTRIC GATE FIELD EFFECT TRANSISTORS; FERROELECTRIC RANDOM ACCESS MEMORY (FRAM); HIGH-DENSITY INTEGRATION; MEMORY ARRAYS; NONDESTRUCTIVE DATA READOUT; V/3-RULE;

RANDOM ACCESS STORAGE;

EID: 21244482079     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.44.2715     Document Type: Conference Paper

References (7)

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