A novel data writing method in a 1T2C-type ferroelectric memory

2002 23rd International Conference on Microelectronics, MIEL 2002 - Proceedings

Volumn 2, Issue , 2002, Pages 517-520

  Ishiwara, H ^a   Yamamoto, S ^a  

^a TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; FERROELECTRIC DEVICES; SPICE;

1T2C-TYPE FERROELECTRIC MEMORY; CELL STRUCTURE; DEVICE PARAMETERS; FERROELECTRIC CAPACITORS; GATE CAPACITANCE; GATE ELECTRODES; SPICE SIMULATIONS; STABLE OPERATION;

MICROELECTRONICS;

EID: 84906685142     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MIEL.2002.1003310     Document Type: Conference Paper

References (5)

1. H. Ishiwara, "Proposal of a Novel Ferroelectric-Gate Field Effect Transistor with Separated Functions for Data Read-Out and Data Storage ", in Extended Abstracts of the 1998 International Conference on Solid State Devices and Materials, Hiroshima, 1998, pp.222-223.
2. S.M. Yoon and H. Ishiwara, "Memory Operations of 1T2CType Ferroelectirc Memory Cell with Excellent Data Retention Characteristics ", IEEE Trans. Electron Devices, 2001, vol. 48, pp. 2002-2008.
3. H. Ishiwara, T. Shimamura, and E. Tokumitsu, "Proposal of a Single-Transistor-Cell-Type Ferroelectric Memory Using an SOI Structure and Experimental Study on the Interference Problem in the Write Operation ", Jpn. J. Appl. Phys., 1997, vol. 36, pp. 1655-1658.
4. T. Tamura, Y. Arimoto, and H. Ishiwara, "A Parallel Element Model for Simulating Switching Response of Ferroelectric Capacitors ", IEI CE Trans. Electron., 2001, vol. E84-C, pp. 785-790.
5. T. Tamura, Y. Arimoto, and H. Ishiwara, "A New Circuit Simulation Model of Ferroelectric Capacitors ", in Extended Abstracts of the 2001 Internat ional Conference on Solid State Devices and Materials, Tokyo, 2001, pp.528-529.