Packaging the Blue Gene/L supercomputer

IBM Journal of Research and Development

Volumn 49, Issue 2-3, 2005, Pages 213-248

  Coteus, Paul ^a   Bickford, H Randall ^a   Cipolla, Thomas M ^a   Crumley, Paul G ^a   Gara, Alan ^a   Hall, Shawn A ^a   Kopcsay, Gerard V ^a   Lanzetta, Alphonso P ^a   Mok, Lawrence S ^a   Rand, Rick ^a   Swetz, Richard ^a   Takken, Todd ^a   La Rocca, Paul ^b   Marroquin, Christopher ^b   Germann, Philip R ^b   Jeanson, Mark J ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BIT ERROR RATE; COMPUTER ARCHITECTURE; CONTROL SYSTEMS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; FIELD PROGRAMMABLE GATE ARRAYS; MICROPROCESSOR CHIPS; PARALLEL PROCESSING SYSTEMS; RELIABILITY; SMART CARDS;

CELLULAR ARCHITECTURE; PARALLEL ARCHITECTURE; PETAFLOP MACHINE; PROCESSORS;

SUPERCOMPUTERS;

EID: 21044453882     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.492.0213     Document Type: Article

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