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Volumn 46, Issue 6, 2002, Pages 675-688

Embedded DRAM design and architecture for the IBM 0.11-μm ASIC offering

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS STORAGE; EMBEDDED SYSTEMS; INTEGRATED CIRCUIT LAYOUT; USER INTERFACES;

EID: 4544337317     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.466.0675     Document Type: Review
Times cited : (23)

References (13)
  • 1
    • 0032203003 scopus 로고    scopus 로고
    • Processor based built-in self test for embedded DRAM
    • November
    • J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, "Processor Based Built-in Self Test for Embedded DRAM," IEEE J. Solid-State Circuits 33, No. 11, 1731-1740 (November 1998).
    • (1998) IEEE J. Solid-state Circuits , vol.33 , Issue.11 , pp. 1731-1740
    • Dreibelbis, J.1    Barth, J.2    Kalter, H.3    Kho, R.4
  • 6
    • 84861239183 scopus 로고
    • "Field Effect Transistor Memory," U.S. Patent 3,387,286, June 4
    • R. H. Dennard, "Field Effect Transistor Memory," U.S. Patent 3,387,286, June 4, 1968.
    • (1968)
    • Dennard, R.H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.