-
1
-
-
0032203003
-
Processor based built-in self test for embedded DRAM
-
November
-
J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, "Processor Based Built-in Self Test for Embedded DRAM," IEEE J. Solid-State Circuits 33, No. 11, 1731-1740 (November 1998).
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, Issue.11
, pp. 1731-1740
-
-
Dreibelbis, J.1
Barth, J.2
Kalter, H.3
Kho, R.4
-
2
-
-
0032202488
-
A configurable DRAM macro design for 2112 derivative organizations to be synthesized using a memory generator
-
November
-
T. Yabe, S. Miyano, K. Sato, M. Wada, R. Haga, O. Wada, M. Enkaku, T. Hojyo, K. Mimoto, M. Tazawa, T. Ohkubo, and K. Numata, "A Configurable DRAM Macro Design for 2112 Derivative Organizations to be Synthesized Using a Memory Generator," IEEE J. Solid-State Circuits 33, No. 11, 1752-1757 (November 1998).
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, Issue.11
, pp. 1752-1757
-
-
Yabe, T.1
Miyano, S.2
Sato, K.3
Wada, M.4
Haga, R.5
Wada, O.6
Enkaku, M.7
Hojyo, T.8
Mimoto, K.9
Tazawa, M.10
Ohkubo, T.11
Numata, K.12
-
3
-
-
0032257657
-
Integration of trench DRAM into a high performance 0.18-μm logic technology with copper BEOL
-
S. Crowder, R. Hannon, H. Ho, D. Sinitsky, S. Wu, K. Winstel, B. Khan, S. R. Stiffler, and S. S. Iyer, "Integration of Trench DRAM into a High Performance 0.18-μm Logic Technology with Copper BEOL," International Electron Devices Meeting, Digest of Technical Papers, 1998, pp. 1017-1020.
-
(1998)
International Electron Devices Meeting, Digest of Technical Papers
, pp. 1017-1020
-
-
Crowder, S.1
Hannon, R.2
Ho, H.3
Sinitsky, D.4
Wu, S.5
Winstel, K.6
Khan, B.7
Stiffler, S.R.8
Iyer, S.S.9
-
5
-
-
0035063915
-
An embedded DRAM hybrid macro with auto signal management and enhanced on chip tester
-
N. Watanabe, F. Morishita, Y. Taito, A. Yamazaki, T. Tanizaki, K. Dosaka, Y. Morooka, F. Igaue, K. Furue, Y. Nagura, T. Komoike, T. Morihara, A. Hachisuka, K. Arimoto, and H. Ozaki, "An Embedded DRAM Hybrid Macro with Auto Signal Management and Enhanced on Chip Tester," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 2001, pp. 388-389, 469.
-
(2001)
IEEE International Solid-state Circuits Conference, Digest of Technical Papers
, pp. 388-389
-
-
Watanabe, N.1
Morishita, F.2
Taito, Y.3
Yamazaki, A.4
Tanizaki, T.5
Dosaka, K.6
Morooka, Y.7
Igaue, F.8
Furue, K.9
Nagura, Y.10
Komoike, T.11
Morihara, T.12
Hachisuka, A.13
Arimoto, K.14
Ozaki, H.15
-
6
-
-
84861239183
-
-
"Field Effect Transistor Memory," U.S. Patent 3,387,286, June 4
-
R. H. Dennard, "Field Effect Transistor Memory," U.S. Patent 3,387,286, June 4, 1968.
-
(1968)
-
-
Dennard, R.H.1
-
8
-
-
19344374536
-
Built-in self test for embedded DRAM
-
West Greenwich, RI
-
J. Dreibelbis, J. Barth, H. Kalter, and R. Kho, "Built-In Self Test for Embedded DRAM," Proceedings of the IEEE North Atlantic Test Workshop, West Greenwich, RI, 1997, pp. 19-27.
-
(1997)
Proceedings of the IEEE North Atlantic Test Workshop
, pp. 19-27
-
-
Dreibelbis, J.1
Barth, J.2
Kalter, H.3
Kho, R.4
-
9
-
-
0032312608
-
How we test siemens' embedded DRAM cores
-
R. McConnell, U. Moller, and D. Richter, "How We Test Siemens' Embedded DRAM Cores," Proceedings of the International Test Conference, 1998, pp. 1120-1125.
-
(1998)
Proceedings of the International Test Conference
, pp. 1120-1125
-
-
McConnell, R.1
Moller, U.2
Richter, D.3
-
11
-
-
0031678265
-
An ASIC library granular DRAM macro with built-in self test
-
J. Dreibelbis, J. Barth, Jr., R. Kho, and T. Kalter, "An ASIC Library Granular DRAM Macro with Built-In Self Test," IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1998, pp. 74-75.
-
(1998)
IEEE International Solid-state Circuits Conference, Digest of Technical Papers
, pp. 74-75
-
-
Dreibelbis, J.1
Barth Jr., J.2
Kho, R.3
Kalter, T.4
-
12
-
-
0026853957
-
A 576K 3.5ns access BiCMOS ECL static ram with array built-in self test
-
April
-
H. A. Bonges III, R. D. Adams, A. J. Allen, R. Flaker, K. S. Gray, E. L. Hedberg, W. T. Holman, G. M. Lattimore, D. A. Lavalette, K. Y. T. Nguyen, and A. L. Roberts, "A 576K 3.5ns Access BiCMOS ECL Static Ram with Array Built-In Self Test," IEEE J. Solid-State Circuits 27, No. 4, 649-656 (April 1992).
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.4
, pp. 649-656
-
-
Bonges III, H.A.1
Adams, R.D.2
Allen, A.J.3
Flaker, R.4
Gray, K.S.5
Hedberg, E.L.6
Holman, W.T.7
Lattimore, G.M.8
Lavalette, D.A.9
Nguyen, K.Y.T.10
Roberts, A.L.11
-
13
-
-
0035680892
-
Embedded DRAM built in self test and methodology for test insertion
-
P. Jakobsen, J. Dreibelbis, G. Pomichter, D. Anand, J. Barth, M. Nelms, J. Leach, and G. Belansek, "Embedded DRAM Built In Self Test and Methodology for Test Insertion," Proceedings of the International Test Conference, 2001, pp. 975-984.
-
(2001)
Proceedings of the International Test Conference
, pp. 975-984
-
-
Jakobsen, P.1
Dreibelbis, J.2
Pomichter, G.3
Anand, D.4
Barth, J.5
Nelms, M.6
Leach, J.7
Belansek, G.8
|