Parallel VLSI architectures for a class of LDPC codes

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 2, Issue , 2002, Pages 93-96

  Kim, Sungwook ^a   Sobelman, Gerald E ^a   Moon, Jaekyun ^a  

^a University of Minnesota   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPUTER SIMULATION; DECODING; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATRIX ALGEBRA; VLSI CIRCUITS;

LOW DENSITY PARITY CHECK CODES; PARALLEL VLSI ARCHITECTURE;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036292755     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2002.1010932     Document Type: Article

References (10)

1. Low density parity check codes
2. Near Shannon limit performance of low density parity check codes
3. Parallel decoding architectures for low density parity check codes
4. A 220mW 1 Gb/s 1024-bit rate-1/2 low density parity check code decoder
5. A low-density generator matrix interpretation of parallel concatenated single bit parity codes
6. Iterative decoding of multi-dimensional concatenated single parity check codes
7. Low density parity check coding for magnetic recording channels with media noise
8. Low density parity check codes for magnetic recording
9. VLSI architectures for iterative decoders in magnetic recording channels
10. On finite precision implementation of low density parity check codes decoder