Characterization and modeling of parasitic emission in deep submicron CMOS

IEEE Transactions on Electromagnetic Compatibility

Volumn 47, Issue 2, 2005, Pages 382-387

  Vrignon, Bertrand ^a   Bendhia, Sonia Delmas ^b   Lamoureux, Enrique ^b   Sicard, Etienne ^b  

^a STMICROELECTRONICS   (France)

^b INSA   (France)

Author keywords

Complementary metal oxide semiconductor (CMOS) technology; Electromagnetic compatability (EMC); Electromagnetic interference (EMI) modeling; On chip sampling

Indexed keywords

ELECTROMAGNETIC COMPATIBILITY; FREQUENCY DOMAIN ANALYSIS; MATHEMATICAL MODELS; SIGNAL INTERFERENCE; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS;

INTERNAL CURRENT SWITCHING; PARASITIC EMISSIONS;

CMOS INTEGRATED CIRCUITS;

EID: 20444498985     PISSN: 00189375     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEMC.2005.847408     Document Type: Article

References (14)

1. The international technology roadmap for semiconductors (2003). [Online]. Available: http://public.itrs.net
2. S. Hayashi and M. Yamada, "EMI noise analysis under ASIC design environment," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 19, no. 11, pp. 1337-1346, Nov. 2000.
3. M. P. Robinson, T. M. Benson, and C. Christopoulos, "Effect of logic family on radiated emissions from digital circuits," IEEE Trans. Electromagn. Compat., vol. 40, no. 3, pp. 288-293, Mar. 1998.
4. EDA roadmap for semiconductors [Online]. Available: http://www.medeaplus. org
5. T. Steinecke, "Design-in for EMC on CMOS large-scale integrated circuits," in Proc. IEEE EMC Int. Symp. Record, vol. 2, 2001, pp. 910-915.
6. T. Steinecke, W. John, H. Koehne, and M. Schmidt, "EMC modeling and simulation on chip level," in Proc. IEEE Int. Symp. Electromagnetic Compatibility, vol. 2, Aug. 2001, pp. 1191-1196.
7. Integrated circuit electromagnetic model (2003, Jun.). [Online]. Available: www.ic-emc.org
8. S. Delmas-Bendhia, F. Caignet, E. Sicard, and M. Roca, "On-chip sampling in CMOS integrated circuits," IEEE Trans. Electromagn. Compat., vol. 41, no. 4, pp. 403-406, Nov. 1999.
9. International Electro-technical Commission, IEC 61967: Integrated Circuits, Measurements of Conducted and Radiated Electromagnetic Emission, 1999.
10. A. Tankielun, P. Kralicek, U. Keller, E. Sicard, and B. Vrignon, "Influence of core optimization and activity for electromagnetic near-field and conducted emissions of CESAME test chip," in Proc. EMC Compo Workshop, Apr. 2004, pp. 95-100.
11. E. Macii, M. Pedram, and F. Somezi, "High-level power modeling, estimation and optimization," IEEE Trans. Computer-Aided Design Integr. Circuits Syst., vol. 17, no. 11, pp. 1061-1079, Nov. 1998.
12. R. Perdriau, M. Ramdani, J.-L. Levant, A. Meresse, and A.-M. Trullemans, "Reusable activity models for EMC prediction in integrated circuits," in Proc. 4th Int. Workshop EMC of ICs, 2004, pp. 32-37.
13. N. Delorme, M. Belleville, and J. Chilo, "Inductance and capacitance analytic formulas for VLSI interconnects," Electron. Lett., vol. 32, no. 11, pp. 996-997, May 1996.
14. H. Grabinski, B. Konrad, and P. Nordholz, "Simple formulas to calculate the line parameters of interconnects on conducting substrates," in Proc. IEEE 7th Topical Meeting Electrical Performance Electronic Packaging (EPEP'98), West Point, NY, Oct. 1998, pp. 223-226.