Piecewise linear model for transmission line with capacitive loading and ramp input

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 6, 2005, Pages 928-936

  Chen, Jun ^a   He, Lei ^a  

^a Department of Civil and Environmental Engineering   (United States)

Author keywords

Inductance; Interconnect modeling; Signal integrity; Transmission line; Very large scale integration (VLSI) interconnect

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC LOADS; ERROR ANALYSIS; INDUCTANCE; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; PIECEWISE LINEAR TECHNIQUES; VLSI CIRCUITS; WAVEGUIDES;

INTERCONNECT MODELING; PIECEWISE LINEAR (PWL) MODEL; SIGNAL INTEGRITY; VERY LARGE SCALE INTEGRATION (VLSI) INTERCONNECTS;

ELECTRIC LINES;

EID: 20444447016     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.847895     Document Type: Article

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