Development of automatic OPC treatment and layout decomposition for double dipole lithography for low-k1 imaging

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5645, Issue , 2005, Pages 21-31

  Chiou, Tsann Bim ^a   Chen, Alek ^a   Hsu, Stephen ^b   Eurlings, Mark ^c   Hendrickx, Eric ^d  

^a ASML Taiwan Ltd   (Taiwan)

^b ASML US Inc   (United States)

^c ASML   (Netherlands)

^d IMEC   (Belgium)

Author keywords

Double dipole lithography (DDL); Image placement error (IPE); Layout decomposition; Optical proximity correction (OPC) treatment; Overlay error; Resolution enhancement technique (RET)

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; IMAGING SYSTEMS; INTEGRATED CIRCUIT MANUFACTURE; MASKS; MATHEMATICAL MODELS; PHASE SHIFT;

DOUBLE DIPOLE LITHOGRAPHY (DDL); IMAGE PLACEMENT ERRORS (IPE); LAYOUT DECOMPOSITION; OPTICAL PROXIMITY CORRECTION (OPC); OVERLAY ERRORS; RESOLUTION ENHANCEMENT TECHNIQUES (RET);

PHOTOLITHOGRAPHY;

EID: 20044368306     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.575989     Document Type: Conference Paper

References (6)

1. M. Eurlings et al, "0.11um Imaging in KrF Lithography Using Dipole Illumination," SPIE v4404, p. 266, 2001
2. S. D. Hsu et al, "Dipole Decomposition Mask Design for Full-Chip Implementation at 100nm Technology Node and Beyond," SPIE v4691, p. 476, 2002
3. S. D. Hsu et al, "65nm Full-chip Implementation Using Double Dipole Lithography," SPIE v5040, p. 215, 2003
4. M. Eurlings et al, "Experimental Verification of a Model Based Decomposition Method for Double Dipole Lithography," SPIEv 5377, p. 1225, 2004
5. T. B. Chiou et al, "The Magnitude of Potential Exposure-Tool-Induced Critical Dimension and Overlay Errors in Double Dipole Lithography for the 65-nm and 45-nm Technology Nodes," Japanese Journal of Applied Physics, V. 43, No. 6B, p. 3672, 2004
6. L. Capodieci et al, "Rule-Based Dipole Partitioning for Electronic Design Layouts," Novel Methodology and Invention Disclosure, 2001