The effect of annealing temperatures on self-aligned replacement (Damascence) TaCN-TaN-stacked gate pMOSFETs

IEEE Transactions on Electron Devices

Volumn 51, Issue 4, 2004, Pages 581-586

  Pan, James ^a   Woo, Christy ^b   Ngo, Minh Van ^b   Xie, James ^b   Matsumoto, David ^b   Murthy, Dakshi ^b   Goo, Jung Suk ^b   Xiang, Qi ^b   Lin, Ming Ren ^b  

^a IBM   (United States)

^b ADVANCED MICRO DEVICES   (United States)

Author keywords

Carbon; Metal gate; pMOSFETs; Replacement; Tantalum

Indexed keywords

ANNEALING; CHEMICAL ACTIVATION; GATES (TRANSISTOR); HIGH TEMPERATURE EFFECTS; PHYSICAL VAPOR DEPOSITION; TANTALUM COMPOUNDS; THERMODYNAMIC STABILITY; THRESHOLD VOLTAGE;

DAMASCENE; IMPACT ACTIVATION ANNEAL; METAL ELECTRODE DEPOSITION; SELF ALIGNED REPLACEMENT; STACKED GATE;

MOSFET DEVICES;

EID: 1942518810     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.825107     Document Type: Article

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