Metal gate NMOSFETs with TaSiN/TaN stacked electrode: Fabricated by a replacement (damascene) technique

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn 2003-January, Issue , 2003, Pages 72-75

  Pan, James ^a   Ngo, Minh Van ^a   Woo, Christy ^a   Goo, Jung Suk ^a   Besser, Paul ^a   Yu, Bin ^a   Xiang, Qi ^a   Lin, Ming Ren ^a  

^a ADVANCED MICRO DEVICES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRODES; INTERFACE STATES; METALS; TEMPERATURE; THRESHOLD VOLTAGE;

GATE ELECTRODES; INTERFACE STATES DENSITY; LOW TEMPERATURES; METAL DEPOSITION; PLASMA DAMAGE; POST-FABRICATION; SUBTHRESHOLD SLOPE; TRANSISTOR PERFORMANCE;

MOSFET DEVICES;

EID: 84944674101     PISSN: 19308868     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTSA.2003.1252555     Document Type: Conference Paper

References (7)

1. Y. Choi, N. Lindert, P. Xuan, S. Tang, D. Ha, E. Anderson, T-J. King, J. Bokor, C. Hu, "Sub-20nm CMOS FinFET Technologies", in IEDM Tech. Dig., 2001, pp. 421-424.
2. R. Chau, J. Kvalieros, B. Doyle, A. Murthy, N. Paulsen, D. Lionberger, D. Barlage, R. Arghavani, B. Roberds and M. Doczy, "A 50nm Depleted-Substrate CMOS Transistor (DST)", in IEDM Tech. Dig., 2001, pp. 621-624.
3. T. Tezuka, N. Sugiyama, T. Mizuno and S. Takagi, "High Performance Strained Si-on-Insulator MOSFETs by Novel Fabrication Processes Utilizing Ge-Condensation Technique " in VLSI Tech. Dig, 2002, pp. 96-97.
4. B. Yu, H. Wang, Q. Xiang, J. An, J. Jeon and M.-R. Lin, "Scaling Towards 35nm Gate Length CMOS", in VLSI Tech. Dig., 2001, pp. 74-75.
5. J. Pan, C. Woo, B Yu, Q. Xiang, M.-R. Lin, "TaSiN and TiSiN With Tunable Work Functions For Metal Gate CMOS Applications", to be submitted.
6. S. Sze, "Physics of Semiconductor Devices", John Wiley and Sons, Inc. New York, NY, 1981, pp. 251.
7. J. Pan, C. Woo, B. Yu, Qi Xiang, M.-R. Lin, "Replacement Metal-Gate NMOSFETs with ALCVD TaN/EP-Cu, PVD Ta, and PVD TaN Electrode", to be submitted.