An event graph based simulation and scheduling analysis of multi-cluster tools

Proceedings - Winter Simulation Conference

Volumn 2, Issue , 2004, Pages 1915-1923

  Ding, Shengwei ^a   Yi, Jingang ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b LAM RESEARCH CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; FUNCTIONS; GRAPHIC METHODS; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; OPTIMIZATION; ROBOTS; SCHEDULING;

CHEMICAL-MECHANICAL PLANARIZATION (CMP) POLISHERS; MULTI-CULSTER TOOLS; SCHEDULING ANALYSIS; SEMICONDUCTOR MANUFACTURING;

COMPUTER SIMULATION;

EID: 17744390222     PISSN: 08917736     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)

1. Dümmler, M. A. 1999. Using Simulation and Genetic Algorithems to Improve Cluster Tool Performance. In Proceedings of the 1999 Winter Simulation Conference, ed. D. T. Sturrock, G. W. Evans, P. A. Farrington, and H. B. Nemhard, 875-879. Piscataway, NJ: Institute of Electrical and Electronics Engineers.
2. Jevtic, D. Method and aparatus for priority based scheduling of wafer processing within a multiple chamber semiconductor wafer processing tool. U.S. Patent 5,928,389, July, 1999.
3. LeBaron, H. T., and R. A. Hendrickson. 2000. Using Emulation to Validate a Cluster Tool Simulation Model. In Proceedings of the 2000 Winter Simulation Conference, ed. P. A. Fishwick, K. Kang, J. A. Joines, and R. R. Barton, 1417-1422. Piscataway, NJ: Institute of Electrical and Electronics Engineers.
4. LeBaron, H. T., and M. Pool. 1994. The Simulation of Cluster Tools: A New Semiconductor Manufacturing Technology. In Proceedings of the 1994 Winter Simulation Conference, ed. D. A. Sadowski, A. F. Seila, J. D. Tew, and S. Manivannan, 907-912. Piscataway, NJ: Institute of Electrical and Electronics Engineers.
5. Nehme, D. A., and N. G. Pierce. 1994. Evaluation the Throughput of Cluster Tools Using Event-graph Simulations. In Proceedings of the 1994 IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 189-192. Cambridge, MA.
6. Pederson, D., and C. Trout. 2002. Demonstrated Benefits of Cluster Tool Simulation. In Proceedings of the 2002 International Conference on Modeling and Analysis of Semiconductor Manufacturing, 84-89. Tempe, AZ.
7. Perkinson, T., P. McLarty, R. Gyurcsik, and R. Cavin. 1994. Single-Wafer Cluster Tool Performance: An Analysis of Throughput. IEEE Trans. on Semiconductor Manufacturing 7 (3): 369-373.
8. Rostami, S., and B. Hamidzadeh. 2002. Optimal Scheduling Techniques for Cluster Tools With Process-Module and Transport-Module Residency Constraints. IEEE Trans. on Semiconductor Manufacturing 15 (3): 341-349.
9. Rostami, S., and B. Hamidzadeh. 2004. An Optimal Residency-Aware Scheduling Technique for Cluster Tools With Buffer Module. IEEE Trans. on Semiconductor Manufacturing 17 (1): 68-73.
10. Rostami, S., B. Hamidzadeh, and D. Camporese. 2001. An Optimal Periodic Scheduler for Dual-Arm Robots in Cluster Tools with Residency Constraints. IEEE Trans. Robot. Automat. 17 (5): 609-618.
11. Schruben, L. W. 2000. SIGMA User's Guide. Berkeley, CA: Department of Industrial Engineering and Operations Research, University of California at Berkeley.
12. Srinivasan, R. 1998. Modeling and Performance Analysis of Cluster Tools Using Petri Nets. IEEE Trans. on Semiconductor Manufacturing 11 (3): 394-403.
13. Venkatesh, S., R. Davenport, P. Foxhoven, and J. Nulman. 1997. A Steady-State Throughput Analysis of Cluster Tools: Dual-Blade Versus Single-Blade Robots. IEEE Trans. on Semiconductor Manufacturing 10 (4): 418-424.
14. Yi, J., D. Song, and S. Ding. 2004. Steady-State Throughput and Scheduling Analysis of Multi-Cluster Tools for Semiconductor Manufacturing Using Decomposition Methods. Working Paper.
15. Zuberek, W. 2001. Timed Petri Nets in Modeling and Analysis of Cluster Tools. IEEE Trans. on Robotics and Automation 17 (5): 562-575.