-
1
-
-
0024733223
-
"Low temperature fabrication of high mobility poly-Si TFT's for large-area LCD's"
-
Sep
-
T. Serikawa, S. Shirai, A. Okamoto, and S. Suyama, "Low temperature fabrication of high mobility poly-Si TFT's for large-area LCD's," IEEE Trans. Electron Devices, vol. 36, no. 9, pp. 1929-1933, Sep. 1989.
-
(1989)
IEEE Trans. Electron Devices
, vol.36
, Issue.9
, pp. 1929-1933
-
-
Serikawa, T.1
Shirai, S.2
Okamoto, A.3
Suyama, S.4
-
2
-
-
0033332475
-
"Low-temperature polysilicon thin film transistor driving with integrated driver for high resolution light emitting polymer display"
-
Dec
-
M. Kimura, I. Yudasaka, S. Kanbe, H. Kobayashi, H. Kiguchi, S. Seki, S. Miyazawa, T. Shimoda, and H. Ohshima, 'Low-temperature polysilicon thin film transistor driving with integrated driver for high resolution light emitting polymer display," IEEE Trans. Electron Devices, vol. 46, no. 12, pp. 2282-2288, Dec. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.12
, pp. 2282-2288
-
-
Kimura, M.1
Yudasaka, I.2
Kanbe, S.3
Kobayashi, H.4
Kiguchi, H.5
Seki, S.6
Miyazawa, S.7
Shimoda, T.8
Ohshima, H.9
-
3
-
-
0022119783
-
"Anormalous leakage current in LPCVD polysilicon MOSFET's"
-
H. G. Fossum, A. Oritz-Conde, H. Shichijo, and S. K. Banerjee, "Anormalous leakage current in LPCVD polysilicon MOSFET's," IEEE Trans. Electron Devices, vol. ED-32, no., pp. 1878-1884, 1985.
-
(1985)
IEEE Trans. Electron Devices
, vol.ED-32
, pp. 1878-1884
-
-
Fossum, H.G.1
Oritz-Conde, A.2
Shichijo, H.3
Banerjee, S.K.4
-
4
-
-
0030214010
-
"Leakage current mechanism in submicron polysilicon thin-film transistors"
-
Aug
-
K. R. Olasupo and M. K. Hatalis, "Leakage current mechanism in submicron polysilicon thin-film transistors," IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1218-1223, Aug. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.8
, pp. 1218-1223
-
-
Olasupo, K.R.1
Hatalis, M.K.2
-
5
-
-
1942520276
-
"A novel self-aligned offset-gated polysilicon TFT using high-k dielectric spacers"
-
Apr
-
Z. Xiong, H. Liu, C. Zhu, and J. K. O. Sin, "A novel self-aligned offset-gated polysilicon TFT using high-k dielectric spacers," IEEE Electron Device Lett., vol. 25, no. 4, pp. 194-195, Apr. 2004.
-
(2004)
IEEE Electron Device Lett.
, vol.25
, Issue.4
, pp. 194-195
-
-
Xiong, Z.1
Liu, H.2
Zhu, C.3
Sin, J.K.O.4
-
6
-
-
0023851207
-
"Characteristics of offset-structure polycrystalline-silicon thin film transistors"
-
Jan
-
K. Tanaka, H. Arai, and S. Kohda, "Characteristics of offset-structure polycrystalline-silicon thin film transistors," IEEE Electron Device Lett., vol. 9, no. 1, pp. 23-25, Jan. 1988.
-
(1988)
IEEE Electron Device Lett.
, vol.9
, Issue.1
, pp. 23-25
-
-
Tanaka, K.1
Arai, H.2
Kohda, S.3
-
7
-
-
0035125016
-
"A novel thin-film transistor with self-aligned field induced drain"
-
Jan
-
H.-C. Lin, C.-M. Yu, C.-Y. Lin, K.-L. Yeh, T.-Y. Huang, and T.-F. Lei, "A novel thin-film transistor with self-aligned field induced drain," IEEE Electron Device Lett., vol. 22, no. 1, pp. 26-28, Jan. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.1
, pp. 26-28
-
-
Lin, H.-C.1
Yu, C.-M.2
Lin, C.-Y.3
Yeh, K.-L.4
Huang, T.-Y.5
Lei, T.-F.6
-
8
-
-
0030211539
-
"The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors"
-
Aug
-
K. R. Olasupo, W. Yarbrough, and M. K. Hatalis, "The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors," IEEE Trans. Electron Devices, vol. 43, no. 8, pp. 1306-1308, Aug. 1996.
-
(1996)
IEEE Trans. Electron Devices
, vol.43
, Issue.8
, pp. 1306-1308
-
-
Olasupo, K.R.1
Yarbrough, W.2
Hatalis, M.K.3
-
9
-
-
2442679485
-
"Influence of field-induced drain on the characteristics of poly-Si thin-film transistor using a self-aligned double spacer process"
-
J. Ahn and O. Kim, "Influence of field-induced drain on the characteristics of poly-Si thin-film transistor using a self-aligned double spacer process," Jpn. J. Appl. Phys., vol. 43, no. 3, pp. 897-900, 2004.
-
(2004)
Jpn. J. Appl. Phys.
, vol.43
, Issue.3
, pp. 897-900
-
-
Ahn, J.1
Kim, O.2
-
10
-
-
0035473960
-
"A novel high-performance polysilicon thin film transistor with a self-aligned thicker sub gate oxide near the drain/source regions"
-
Oct
-
K. M. Chang, Y. H. Chung, G. M. Lin, J. H. Lin, and C. G. Deng, "A novel high-performance polysilicon thin film transistor with a self-aligned thicker sub gate oxide near the drain/source regions," IEEE Electron Device Lett., vol. 22, no. 10, pp. 472-474, Oct. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.10
, pp. 472-474
-
-
Chang, K.M.1
Chung, Y.H.2
Lin, G.M.3
Lin, J.H.4
Deng, C.G.5
-
11
-
-
0035506834
-
"A new poly-Si TFT structure with air cavities at the gate-oxide edges"
-
Nov
-
M. Lee, S. Jung, I. Song, and M. Han, "A new poly-Si TFT structure with air cavities at the gate-oxide edges," IEEE Electron Device Lett. vol. 22, no. 11, pp. 541-549, Nov. 2001.
-
(2001)
IEEE Electron Device Lett.
, vol.22
, Issue.11
, pp. 541-549
-
-
Lee, M.1
Jung, S.2
Song, I.3
Han, M.4
-
12
-
-
0037600567
-
"A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation"
-
Mar
-
J. Choe, C. Lee, S. Kim, S. Kim, S. Lee, J. Lee, Y.-G. Shin, D. Park, and K. Kim, "A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation," IEEE Electron Device Lett, vol. 24, no. 3, pp. 195-197, Mar. 2003.
-
(2003)
IEEE Electron Device Lett.
, vol.24
, Issue.3
, pp. 195-197
-
-
Choe, J.1
Lee, C.2
Kim, S.3
Kim, S.4
Lee, S.5
Lee, J.6
Shin, Y.-G.7
Park, D.8
Kim, K.9
|