A 22-nm damascene-gate MOSFET fabrication with 0.9-nm EOT and local channel implantation

IEEE Electron Device Letters

Volumn 24, Issue 3, 2003, Pages 195-197

  Choe, Jeong Dong ^a   Lee, Chang Sub ^a   Kim, Sung Ho ^a   Kim, Sung Min ^a   Lee, Shin Ae ^a   Lee, Ju Won ^a   Shin, You Gyun ^a   Park, Donggun ^a   Kim, Kinam ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

0.9 nm EOT; 22 nm gate length; CMOS; Damascene scheme; Local channel implantation; Spike anneal

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; GATES (TRANSISTOR); HOT CARRIERS; ION IMPLANTATION; MOSFET DEVICES; POLYSILICON; RAPID THERMAL ANNEALING; SILICON WAFERS;

BLANKET CHANNEL IMPLANTATION; DAMASCENE GATE; LOCAL CHANNEL IMPLANTATION; SOURCE-DRAIN EXTENSION; SPIKE ANNEAL;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0037600567     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.811401     Document Type: Letter

References (7)

1. R. Chau, "30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays," in IEDM Tech. Dig., 2000, pp. 45-48.
2. H. Wakabayashi, "45 nm gate length CMOS technology and beyond using steep halo," in IEDM Tech. Dig., 2000, pp. 49-52.
3. Y. Taur, "25 nm CMOS design considerations," in IEDM Tech. Dig., 1998, pp. 789-792.
4. B. Yu, "Scaling toward 35 nm gate length CMOS," in VLSI Symp. Tech. Dig, 2001, pp. 9-10.
5. Q. Xiang, "High performance sub-50 nm CMOS with advanced gate stack," in VLSI Symp. Tech. Dig, 2001, pp. 23-24.
6. T replacement gate CMOS with KrF lithography," in IEDM Tech. Dig., 2000, pp. 53-56.
7. H.-H. Vuong et al., "Design of 25-nm SALVO PMOS devices," IEEE Electron Device Lett., vol. 21, pp. 248-250, May 2000.