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Volumn 46, Issue 12, 1999, Pages 2282-2288

Low-temperature polysilicon thin-film transistor driving with integrated driver for high-resolution light emitting polymer display

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; DISPLAY DEVICES; ELECTRIC CONDUCTANCE; ELECTRIC POTENTIAL; OPTICAL MATERIALS; POLYMERS; SEMICONDUCTING SILICON;

EID: 0033332475     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.808054     Document Type: Article
Times cited : (162)

References (16)
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    • R. H. Friend, "Organic electroluminescent displays," in SID Seminar Lecture Notes, 1998, vol. 2, F-l, pp. 1-27.
    • SID Seminar Lecture Notes
    • Friend, R.H.1
  • 12
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    • "New degradation phenomenon in wide channel poly-Si TFT's fabricated by low temperature process," in
    • 1996, pp. 781-784.
    • S. Inoue and H. Ohshima, "New degradation phenomenon in wide channel poly-Si TFT's fabricated by low temperature process," in IEDM Tech. Dig., 1996, pp. 781-784.
    • IEDM Tech. Dig.
    • Inoue, S.1    Ohshima, H.2
  • 13
    • 84886448003 scopus 로고    scopus 로고
    • "Analysis of threshold voltage shift caused by bias stress in low temperature poly-Si TFT's," in
    • 1997, pp. 527-530.
    • S. Inoue, H. Ohshima, and T. Shimoda, "Analysis of threshold voltage shift caused by bias stress in low temperature poly-Si TFT's," in IEDM Tech. Dig., 1997, pp. 527-530.
    • IEDM Tech. Dig.
    • Inoue, S.1    Ohshima, H.2    Shimoda, T.3
  • 14
    • 0032049286 scopus 로고    scopus 로고
    • "Differentiation of effects due to grain and grain boundary traps in laser annealed poly-Si thin-film transistors
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    • G. A. Armstrong, S. Uppal, S. D. Brotherton, and J. R. Ayres, "Differentiation of effects due to grain and grain boundary traps in laser annealed poly-Si thin-film transistors," Jpn. J. Appl. Phys., vol. 37, pp. 1721-1726, 1998.
    • " Jpn. J. Appl. Phys.
    • Armstrong, G.A.1    Uppal, S.2    Brotherton, S.D.3    Ayres, J.R.4
  • 15
    • 33749879978 scopus 로고    scopus 로고
    • "Numerical TFT model for circuit simulation using spline interpolation with transformation by
    • 1998, pp. 181-184.
    • M. Kimura, T. Ozawa, K. Ozawa, and H. Ohshima, "Numerical TFT model for circuit simulation using spline interpolation with transformation by y = x + log(x)," in Dig, Tech. Papers AM-LCD, 1998, pp. 181-184.
    • Y = X + Log(x)," in Dig, Tech. Papers AM-LCD
    • Kimura, M.1    Ozawa, T.2    Ozawa, K.3    Ohshima, H.4
  • 16
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    • M. Kimura, T. Ozawa, and H. Ohshima, "Simulation of horizontal crosstalk in point-at-time scheme with matrix parametric model," in Dig. Tech. Papers AM-LCD, 1996, pp. 317-320.
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    • Kimura, M.1    Ozawa, T.2    Ohshima, H.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.