Impact of Gate-to-Source/Drain Overlap Length on 80-nm CMOS Circuit Performance

IEEE Transactions on Electron Devices

Volumn 51, Issue 3, 2004, Pages 409-414

  Maitra, Kingsuk ^a   Bhat, Navakanta ^b  

^a North Carolina State University   (United States)

^b INDIAN INSTITUTE OF SCIENCE   (India)

Author keywords

Circuit; CMOS; Gate; Mixed mode; Series resistance; Source drain overlap

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC FIELD EFFECTS; ELECTRIC INVERTERS; ELECTRIC RESISTANCE; ERROR ANALYSIS; GATES (TRANSISTOR); HOT CARRIERS; LEAKAGE CURRENTS; SEMICONDUCTOR DOPING; SWITCHING CIRCUITS; THRESHOLD VOLTAGE;

MIXED MODES; SERIES RESISTANCE; SOURCE/DRAIN OVERLAP;

CMOS INTEGRATED CIRCUITS;

EID: 1642286781     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.822347     Document Type: Article

References (11)

1. S. Thompson, P. Packan, T. Ghani, M. Stettler, M. Alavi, I. Post, S. Tyagi, S. Ahmed, S. Yang, and M. Bohr, "Source/drain extension scaling for 0.1 μm and below channel length MOSFETs," in VLSI Tech. Dig., 1998, pp. 132-133.
2. N. Yang, W. K. Hensen, and J. J. Wortman, "A comparative study of gate direct tunneling and drain leakage currents in N-MOSFETs with sub-2-nm gate oxides," IEEE Trans. Electron Devices, vol. 47, pp. 1636-1644, Nov. 2000.
3. K. N. Yang, H. T. Huang, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, D. C. H. Yu, and M. S. Liang, "Characterization and modeling of edge direct tunneling (EDT) leakage in ultrathin gate oxide MOSFETs," IEEE Trans. Electron Devices, vol. 48, pp. 1159-1164, Oct. 2001.
4. G. Timp et al., "Low leakage, ultra-thin gate oxides for extremely high performance sub-100-nm nMOSFETs," in IEDM Tech. Dig., 1997, p. 930.
5. S. Tiwari, J. J. Welser, D. Dimaria, and F. Rana, "Currents, surface potentials, and defect generation in 1.2-1.5 nm oxide MOSFETs," in Proc. Annu. Device Research Conf., vol. 56, 1998, pp. 12-13.
6. K. Maitra and N. Bhat, "An analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in nMOSFETs," J. Appl. Phys., vol. 93, pp. 1064-1068, 2003.
7. C.-H. Choi, K.-Y. Nam, Z. Yu, and R. W. Dutton, "Impact of gate direct tunneling current on circuit performance: A simulation study," IEEE Trans. Electron Devices, vol. 48, pp. 2823-2829, Dec., 2001.
8. M. Y. Kwong, R. Kasnavi, P. Griffin, J. D. Plummer, and R. W. Dutton, "Impact of lateral source/drain abruptness on device performance," IEEE Trans. Electron Devices, vol. 49, pp. 1882-1890, Dec. 2002.
9. "Integrated Systems Engineering,", Zurich, Switzerland, ISE TCAD 6.1.
10. C.-H. Choi, J.-S. Goo, Z. Yu, and R. W. Dutton, "Shallow source/drain extension effects on external resistance in sub-0.1μm MOSFETs," IEEE Trans. Electron Devices, vol. 47, pp. 655-658, 2000.
11. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices. Cambridge, U.K.: Cambridge Univ. Press, 1998.