Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 403-408

  Pant, Pankaj ^a   De, Vivek ^a   Chatterjee, Abhijit ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; LEAKAGE CURRENTS; MINIMIZATION OF SWITCHING NETS; MOSFET DEVICES; VLSI CIRCUITS;

CLOCK FREQUENCY; CMOS LOGIC NETWORK; POWER CONSUMPTION; POWER DISSIPATION; SUPPLY VOLTAGE;

LOGIC CIRCUITS;

EID: 0030681185     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/266021.266181     Document Type: Conference Paper

References (12)