System-level interconnect architecture exploration for custom memory organizations

Proceedings of the International Symposium on System Synthesis

Volumn , Issue , 2001, Pages 13-18

  Van Meeuwen, Tycho ^a   Vandecappelle, Arnout ^a   Van Zelst, Allert ^b   Catthoor, Francky ^a,c   Verkest, Diederik ^a  

^a IMEC   (Belgium)

^b Agere Systems   (Netherlands)

^c UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPUTER AIDED SOFTWARE ENGINEERING; LARGE SCALE SYSTEMS; SOFTWARE PROTOTYPING; TIME DIVISION MULTIPLEXING;

MEMORY BANDWIDTH;

DATA STORAGE EQUIPMENT;

EID: 0034790116     PISSN: 10801820     EISSN: None     Source Type: Journal    
DOI: 10.1145/500001.500005     Document Type: Article

References (17)

1. Allocation of multiport memories in data path synthesis
2. Interface optimization for concurrent systems under timing constraints
3. Architectural power optimization by bus splitting
4. Performance-driven interconnection optimization for microarchitecture synthesis
5. A configurable multiprocessor system for DSP behavioral simulation
6. Allocation of multiport memories for hierarchical data streams
7. Power optimisation and analysis of a Digital Audio Broadcast (DAB) reciever
8. An algorithm for array variable clustering
9. A graph-theoretic approach for register file based synthesis
10. Efficient general-purpose image compression with binary tree predictive coding
11. Low power multi-module, multi-port memory design for embeddes systems
12. Data path synthesis
13. Getting to the bottom of deep submicron
14. Guaranteeing on- and off-chip communication in embedded systems
15. Global multimedia system design exploration using accurate memory organization feedback
16. Minimizing the required memory bandwidth in VLSI system realizations